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NE23300

California Eastern
Part Number NE23300
Manufacturer California Eastern
Description SUPER LOW NOISE HJ FET
Published Aug 9, 2014
Detailed Description SUPER LOW NOISE HJ FET (SPACE QUALIFIED) FEATURES • VERY LOW NOISE FIGURE: 0.75 dB typical at 12 GHz Optimum Noise Figur...
Datasheet PDF File NE23300 PDF File

NE23300
NE23300

Overview
SUPER LOW NOISE HJ FET (SPACE QUALIFIED) FEATURES • VERY LOW NOISE FIGURE: 0.
75 dB typical at 12 GHz Optimum Noise Figure, NFOPT (dB) NE23300 NOISE FIGURE & ASSOCIATED GAIN vs.
FREQUENCY VDS = 2 V, IDS = 10 mA 4.
5 4.
0 3.
5 3.
0 NF 2.
5 2.
0 1.
5 1.
0 0.
5 0 1 10 40 16 14 12 10 8 6 GA 22 20 18 • HIGH ASSOCIATED GAIN: 10.
5 dB Typical at 12 GHz • GATE LENGTH: 0.
3 µm • GATE WIDTH: 280 µm DESCRIPTION The NE23300 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create a two-dimensional electron gas layer with very high electron mobility.
Its excellent low noise figure and high associated gain make it suitable for space applications.
NEC's stringent quality assurance and test procedures assure the highest reliability and performance.
Frequency, f (GHz) ELECTRICAL CHARACTERISTICS (TA = 25°C) PART NUMBER PACKAGE OUTLINE SYMBOLS NFOPT1 PARAMETERS AND CONDITIONS Noise Figure, VDS = 2 V, ID = 10 mA, f = 4 GHz f = 12 GHz Associated Gain, VDS = 2 V, ID = 10 mA, f = 4 GHz f = 12 GHz Output Power at 1 dB Gain Compression Point, f = 12 GHz VDS = 2 V, IDS = 10 mA VDS = 2 V, IDS = 20 mA Gain at P1dB, f = 12 GHz VDS = 2 V, IDS = 10 mA VDS = 2 V, IDS = 20 mA Saturated Drain Current, VDS = 2 V, VGS = 0 V Pinch-off Voltage, VDS = 2 V, ID = 100 µA Transconductance, VDS = 2 V, ID = 10 mA Gate to Source Leakage Current, VGS = -5 V Thermal Resistance (Channel to Case) UNITS dB dB dB dB dBm dBm dB dB mA V mS µA °C/W 15 -2.
0 45 MIN NE23300 00 (Chip) TYP 0.
35 0.
75 15.
0 10.
5 11.
2 12.
0 11.
8 12.
8 40 -0.
8 70 0.
5 10 260 80 -0.
2 MAX 1.
0 GA1 10.
0 P1dB G1dB IDSS VP gm IGSO RTH(CH-C)2 Notes: 1.
RF performance is determined by packaging and testing 10 samples per wafer.
Wafer rejection criteria for standard devices is 2 rejects for 10 samples.
2.
Chip mounted on infinite heat sink.
California Eastern Laboratories Associated Gain, GA (dB) NE23300 ABSOLUTE MAXIMUM RATINGS1 (TA = 25°C) SYMBOLS VDS VGS IDS TCH TSTG PT PARAMETERS Drain to Source...


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