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LatticeXP2

Lattice Semiconductor
Part Number LatticeXP2
Manufacturer Lattice Semiconductor
Description FPGA fabric
Published Aug 20, 2014
Detailed Description LatticeXP2™ Family Data Sheet DS1009 Version 01.8, January 2012 LatticeXP2 Family Data Sheet Introduction January 2012 ...
Datasheet PDF File LatticeXP2 PDF File

LatticeXP2
LatticeXP2

Overview
LatticeXP2™ Family Data Sheet DS1009 Version 01.
8, January 2012 LatticeXP2 Family Data Sheet Introduction January 2012 Data Sheet DS1009 Features  flexiFLASH™ Architecture • • • • • • Instant-on Infinitely reconfigurable Single chip FlashBAK™ technology Serial TAG memory Design security  Flexible I/O Buffer • sysIO™ buffer supports: – LVCMOS 33/25/18/15/12; LVTTL – SSTL 33/25/18 class I, II – HSTL15 class I; HSTL18 class I, II – PCI – LVDS, Bus-LVDS, MLVDS, LVPECL, RSDS  Live Update Technology • TransFR™ technology • Secure updates with 128 bit AES encryption • Dual-boot with external SPI  Pre-engineered Source Synchronous Interfaces • DDR / DDR2 interfaces up to 200 MHz • 7:1 LVDS interfaces support display applications • XGMII  sysDSP™ Block  Density And Package Options • 5k to 40k LUT4s, 86 to 540 I/Os • csBGA, TQFP , PQFP , ftBGA and fpBGA packages • Density migration supported • Three to eight blocks for high performance  Multiply and Accumulate • 12 to 32 18x18 multipliers • Each block supports one 36x36 multiplier or four 18x18 or eight 9x9 multipliers • Up to 885 Kbits sysMEM™ EBR • Up to 83 Kbits Distributed RAM  Flexible Device Configuration • SPI (master and slave) Boot Flash Interface • Dual Boot Image supported • Soft Error Detect (SED) macro embedded  Embedded and Distributed Memory  sysCLOCK™ PLLs • Up to four analog PLLs per device • Clock multiply, divide and phase shifting Table 1-1.
LatticeXP2 Family Selection Guide Device LUTs (K) Distributed RAM (KBits) EBR SRAM (KBits) EBR SRAM Blocks sysDSP Blocks 18 x 18 Multipliers VCC Voltage GPLL Max Available I/O Packages and I/O Combinations 132-Ball csBGA (8 x 8 mm) 144-Pin TQFP (20 x 20 mm) 208-Pin PQFP (28 x 28 mm) 256-Ball ftBGA (17 x17 mm) 484-Ball fpBGA (23 x 23 mm) 672-Ball fpBGA (27 x 27 mm) 86 100 146 172 86 100 146 201 XP2-5 5 10 166 9 3 12 1.
2 2 172 XP2-8 8 18 221 12 4 16 1.
2 2 201  System Level Support • IEEE 1149.
1 and IEEE 1532 Compliant • On-chip oscillator for initia...


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