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CY28351

Part Number	CY28351
Manufacturer	Cypress Semiconductor
Description	Differential Clock Buffer/Driver
Published	Aug 31, 2014
Detailed Description	CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM...
Datasheet	CY28351 PDF File

Overview

CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the outputs to the clock input • Conforms to the DDRI specification • Spread Aware for electromagnetic interference (EMI) reduction • 48-pin SSOP package Description This PLL clock buffer is designed for 2.
5-VDD and 2.
5-AVDD operation and differential outputs levels.
This device is a zero delay buffer that distributes a clock input ...

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