DatasheetsPDF.com

CY7C0833V

Cypress Semiconductor
Part Number CY7C0833V
Manufacturer Cypress Semiconductor
Description Synchronous Dual-Port RAM
Published Sep 3, 2014
Detailed Description CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dua...
Datasheet PDF File CY7C0833V PDF File

CY7C0833V
CY7C0833V

Overview
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.
3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM PRELIMINARY CY7C0837V CY7C0830V/CY7C0831V CY7C0832V/CY7C0833V FLEx18TM 3.
3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM Features • True dual-ported memory cells that allow simultaneous access of the same memory location • Synchronous pipelined operation • Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit devices • Pipelined output mode allows fast operation • 0.
18-micron CMOS for optimum speed and power • High-speed clock to data access • 3.
3V low power — Active as low as 225 mA (typ) • • • • • • • • — Standby as low as 55 mA (typ) Mailbox function for message passing Global master reset Separate byte enables on both ports Commercial and industrial temperature ranges IEEE 1149.
1-compatible JTAG boundary scan 144-ball FBGA (13 mm × 13 mm) (1.
0 mm pitch) 120TQFP (14 mm x 14 mm x 1.
4 mm) Counter wrap around control — Internal mask register controls counter wrap-around — Counter-interrupt flags to indicate wrap-around — Memory block retransmit operation • Counter readback on address lines • Mask register readback on address lines • Dual Chip Enables on both ports for easy depth expansion Functional Description The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit pipelined, synchronous, true dual-port static RAMs that are high-speed, low-power 3.
3V CMOS.
Two ports are provided, permitting independent, simultaneous access to any location in memory.
The result of writing to the same location by more than one port at the same time is undefined.
Registers on control, address, and data lines allow for minimal set-up and hold time.
During a Read operation, data is registered for decreased cycle time.
Each port contains a burst counter on the input address register.
After externally loading the counter with the initial address, the counter will increment the address internally (more details to follow).
The interna...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)