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0IHYL-0047A

LG
Part Number 0IHYL-0047A
Manufacturer LG
Description TFT-LCD Timing Controller
Published Sep 30, 2014
Detailed Description SPECIFICATION FOR APPROVAL ( ) Preliminary Specification (¡Ü) Final Specification Title BUYER MODEL FORT_REV(HS503022) ...
Datasheet PDF File 0IHYL-0047A PDF File

0IHYL-0047A
0IHYL-0047A

Overview
SPECIFICATION FOR APPROVAL ( ) Preliminary Specification (¡Ü) Final Specification Title BUYER MODEL FORT_REV(HS503022) TFT-LCD Timing Controller SUPPLIER MODEL LG Part Number LG.
Philips LCD Co.
, Ltd.
FORT_REV(HS503022) 0IHYL-0047A SIGNATURE DATE SIGNATURE S.
H.
Kang / G.
Manager C.
H.
Kyung / G.
Manager REVIEWED BY J.
S.
Baek / Manager DATE / / J.
D.
Kim / Manager PREPARED BY Suny Kwon / Engineer / K.
J.
Lee / Engineer Please return 1 copy for your confirmation with your signature and comments.
Products Engineering Dept.
LG.
Philips LCD Co.
, Ltd Ver.
1.
1 SEP.
24.
2003 TFT-LCD Timing Controller P/N : 0IHYL-0047A Contents No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Cover Contents Record of Revisions General Description Function Feature Pin Diagram Block Diagram Main Function Description Pin Configuration Signal Description Electrical Specification Screen Display Range MODE Setting DIV, HSY, HSYSC, FCLKO ,FCLKOO Generation Horizontal Display Position Vertical Display Method(NTSC) Vertical Display Method(PAL) Control Option Package Application Circuit Application Notes ITEM Page 1 2 3 3 4 4 5 6 7 8,9,10 11 12 13,14 15 16 17 18 19 20,21 22,23,24 25 ~ 30 Ver.
1.
1 1/30 TFT-LCD Timing Controller P/N : 0IHYL-0047A Record of Revisions Rev.
No.
1.
0 1.
1 1.
1 Rev.
Date Aug.
20.
2003 Sep.
24.
2003 Page 22 ~ 24 25 ~ 30 18.
Application Circuit 19.
Application Notes [Correction ] [Correction ] Description First Draft (Preliminary) Ver.
1.
1 2/30 TFT-LCD Timing Controller P/N : 0IHYL-0047A 1.
General description FORT_REV IC, which is developed by LG.
Philips LCD, is timing controller controlling 6.
5” wide TFT-LCD module.
It is improved LG first ASIC version FORT(0IHYL-0043A).
2.
Function It uses 23.
9MHz input clock, and creates the divide signal for comparing PLL phase.
1) Outside of Controller IC, it is composed PLL circuit with additional VCO, LPF, pulls the sync signal of PAL, NTSC into CSY pin and it is used for creating MCLK by PDP signal with DIV signal whic...


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