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K4D261638K

Samsung
Part Number K4D261638K
Manufacturer Samsung
Description 128Mbit GDDR SDRAM
Published Oct 9, 2014
Detailed Description K4D261638K 128M GDDR SDRAM 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision...
Datasheet PDF File K4D261638K PDF File

K4D261638K
K4D261638K

Overview
K4D261638K 128M GDDR SDRAM 128Mbit GDDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.
3 July 2007 Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1.
For updates or additional information about Samsung products, contact your nearest Samsung office.
2.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
- 1 /19 - Rev.
1.
3 July 2007 K4D261638K Revision History Revision 0.
0 1.
0 1.
1 1.
2 1.
3 Month January September October November July Year 2006 2006 2006 2006 2007 - Target Spec - Defined target specification - Added the Current Spec - Added the IBIS Data - Added and Revised the IBIS Data - Added power up comment - Revised voltage comment of power up sequence History 128M GDDR SDRAM - 2 /19 - Rev.
1.
3 July 2007 K4D261638K 128M GDDR SDRAM 2M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL 1.
0 FEATURES • 2.
5V + 5% power supply for device operation • 2.
5V + 5% power supply for I/O interface • SSTL_2 compatible inputs/outputs • 4 banks operation • MRS cycle with address key programs -.
Read latency 2,3(clock) -.
Burst length (2, 4 and 8) -.
Burst type (sequential & interleave) • All inputs except data & DM are sampled at the positive going edge of the system clock ...


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