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EDE1108AJBG-8E-F

Part Number	EDE1108AJBG-8E-F
Manufacturer	Elpida Memory
Description	1G bits DDR2 SDRAM
Published	Oct 13, 2014
Detailed Description	DATA SHEET 1G bits DDR2 SDRAM EDE1108AJBG (128M words × 8 bits) EDE1116AJBG (64M words × 16 bits) Specifications • Dens...
Datasheet	EDE1108AJBG-8E-F PDF File

Overview

DATA SHEET 1G bits DDR2 SDRAM EDE1108AJBG (128M words × 8 bits) EDE1116AJBG (64M words × 16 bits) Specifications • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (EDE1108AJBG)  8M words × 16 bits × 8 banks (EDE1116AJBG) • Package  60-ball FBGA (EDE1108AJBG)  84-ball FBGA (EDE1116AJBG)  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.
8V ± 0.
1V • Data rate  800Mbps (max.
) • 1KB page size (EDE1108AJBG)  Row address: A0 to A13  Column address: A0 to A9 • 2KB page size (EDE1116AJBG)  Row address: A0 to A12  Column address: A0 to A9 • Eight internal banks for concurrent operation • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • Burst type (BT):  Sequential (4, 8)  Interleave (4, 8) • /CAS Latency (CL): 3, 4, 5, 6 • Precharge: auto precharge option for each burst access • Driver strength: normal, weak • Refresh: auto-refresh, self-refresh Features • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture • Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • Posted /CAS by programmable additive latency for better command and data bus efficiency • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation • Off-Chip Driver (OCD) impedance adjustment is not supported.
• Refresh cycles: 8192 cycles/64ms  Average refresh period 7.
8µs at 0°C ≤ TC ≤ +85°C 3.
9µs at +85°C < TC ≤ +95°C • Operating case temperature range  TC = 0°C to +95°C Document No.
E173...

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