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HMP31GP7AFR4C-S5

Hynix
Part Number HMP31GP7AFR4C-S5
Manufacturer Hynix
Description 240pin Registered DDR2 SDRAM DIMMs based on 2Gb
Published Oct 18, 2014
Detailed Description 240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A This Hynix Registered Dual In-Line Memory Module (DIMM) series...
Datasheet PDF File HMP31GP7AFR4C-S5 PDF File

HMP31GP7AFR4C-S5
HMP31GP7AFR4C-S5

Overview
240pin Registered DDR2 SDRAM DIMMs based on 2Gb version A This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 2Gb version A DDR2 SDRAMs in Fine Ball Grid Array (FBGA) packages on a 240pin glass-epoxy substrate.
This Hynix 2Gb version A based Registered DDR2 DIMM series provide a high performance 8 byte interface in 5.
25" width form factor of industry standard.
It is suitable for easy interchange and addition.
FEATURES • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.
8V +/0.
1V Power Supply All inputs and outputs are compatible with SSTL_1.
8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) • • • • • • • • Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60 ball(x4/x8) 133.
35 x 30.
00 mm form factor RoHS compliant • • • • • • ORDERING INFORMATION Part Name HMP31GP7AFR4C - Y5/S5/S6 Density 8GB Organization 1G X 72 # of DRAMs 36 # of ranks 2 Parity Support O This document is a general product description and is subject to change without notice.
Hynix Semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.
1 / Jan.
2009 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS Y5 (DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP 400 533 667 5-5-5 S6 (DDR2-800) 533 667 800 6-6-6 S5 (DDR2-800) 400 533 800 5-5-5 Unit Mbps Mbps Mbps Mbps tCK ADDRESS TABLE Density Organization 8GB 1G x 72 Ranks 2 SDRAMs 512Mb x 4 # of DRAMs 36 # of row/bank/column Address 15(A0~A14)/3(BA0~BA2)/11(A0~A9,A11) Refresh Method 8K / 64ms Rev.
0.
1 / Jan.
2009 2 1240pin Registered DDR2 SDRAM DIMMs Input/Output Functional Description Symbol CK0 Type IN Polarity Positive Edge...


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