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HC2510

Part Number	HC2510
Manufacturer	Hynix Semiconductor
Description	Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications
Published	Mar 23, 2005
Detailed Description	HC2510C HC2510C Features l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications S...
Datasheet	HC2510 PDF File

Overview

HC2510C HC2510C Features l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev.
1.
2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network Required External Feedback (FBIN) Pin is Used to Synchronize the Outputs to the Clock Input Separate Output Enable for Each Output Bank Operates at 3.
3 V Vcc 125 MHz Maximum Frequency On-chip Series Damping Resistors Support Spread Spectrum Clock(SSC) Synthesizers ESD Protection Exceeds 3000 V per MIL-STD883, Method 3015 ; Exceeds 350 V Using Machine Model ( C = 200 pF, R = 0 ) Latch-Up Performance Exceeds 400 mA per JESD 17 Packaged in Plastic 24-Pin Thin Shrink SmallOutline Package General Description The HC2510C is a low-skew, low jitter, phaselocked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM.
The HC2510C operates at 3.
3V Vcc and provides integrated series-damping resistors that...

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HC2509C Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications - Hynix Semiconductor
HC2510 Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications - Hynix Semiconductor

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