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HCF40100B

STMicroelectronics
Part Number HCF40100B
Manufacturer STMicroelectronics
Description 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER
Published Mar 23, 2005
Detailed Description HCC/HCF40100B 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER . . . . . . . . . . . FULLY STATIC OPERATION SHIFT LEFT/SHIFT ...
Datasheet PDF File HCF40100B PDF File

HCF40100B
HCF40100B

Overview
HCC/HCF40100B 32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER .
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FULLY STATIC OPERATION SHIFT LEFT/SHIFT RIGHT CAPABILITY MULTIPLE PACKAGE CASCADING RECIRCULATE CAPABILITY LIFO OR FIFO CAPABILITY STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENo TATIVE STANDARD N .
13A, ”STANDARD SPECIFICATIONS FOR DESCRIPTION OF ”B” SERIES CMOS DEVICES” data in the 32nd stage is shifted into the first stage when the LEFT/RIGHT CONTROL is low and from the 1st stage to the 32nd stage when the LEFT/RIGHT CONTROL is high.
EY (Plastic Package) F (Ceramic Frit Seal Package) DESCRIPTION The HCC40100B (extended temperature range) and HCF40100B (intermediate temperature range) are monolithic integrated circuits, available in 16lead dual in-line plastic or ceramic package and plastic micro package.
The HCC/HCF40100B is a 32-stage shift register containing 32 D-type masterslave flip-flops.
The data present at the SHIFTRIGHT INPUT is transferred into the first register stage synchronously with the positive CLOCK edge, provided the LEFT/RIGHT CONTROL is at a low level, the RECIRCULATE CONTROL is at a high level, and the CLOCK INHIBIT is low.
If the LEFT/RIGHT CONTROL is at a high level and the RECIRCULATE CONTROL is also high, data at the SHIFT-LEFT INPUT is transferred into the 32nd register stage synchronously with the positive CLOCK transition, provided the CLOCK INHIBIT is low.
The state of the LEFT/RIGHT CONTROL, RECIRCULATE CONTROL, and CLOCK INHIBIT should not be changed when the CLOCK is high.
Data is shifted one stage left or one stage right depending on the state of the LEFT/RIGHT CONTROL, synchronously with the positive CLOCK edge.
Data clocked into the first or 32nd register states is available at the SHIFT-LEFT or SHIFT-RIGHT OUTPUT respectively, on the next...


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