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R7S910118CBG

Renesas
Part Number R7S910118CBG
Manufacturer Renesas
Description 450MHz / 600MHz MCU
Published Dec 3, 2014
Detailed Description Preliminary Datasheet Specifications in this document are tentative and subject to RZ/T1 Group R01DS0228EJ0060 Rev.0....
Datasheet PDF File R7S910118CBG PDF File

R7S910118CBG
R7S910118CBG

Overview
Preliminary Datasheet Specifications in this document are tentative and subject to RZ/T1 Group R01DS0228EJ0060 Rev.
0.
60 Nov 14, 2014 450 MHz/600MHz, MCU with ARM Cortex®-R4F and -M3*1, on-chip FPU, 747/996 DMIPS, up to 1 Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT*1, USB 2.
0 high-speed, CAN, various communications interfaces such as an SPI multi-I/O bus controller, ∆Σ interface, safety functions, encoder interfaces*1, and security functions*1 Features ■ On-chip 32-bit ARM Cortex-R4F processor  High-speed realtime control with maximum operating frequency of 450/600 MHz Capable of 747/996 DMIPS (in operation at 450/600 MHz)  On-chip 32-bit ARM Cortex-R4F (revision r1p4)  Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes  Instruction cache/data cache with ECC: 8 Kbytes per cache  High-speed interrupt  The FPU supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at singleprecision and double-precision.
 Harvard architecture with 8-stage pipeline  Supports the memory protection unit (MPU)  ARM CoreSight architecture, includes support for debugging through JTAG and SWD interfaces ■ (Oinn-pcrhoidpu3c2ts-biint cAoRrpMoCraotrintegxa-Mn3Rp-IrNoceensgsinoer )  150-MHz operating frequency  On-chip 32-bit ARM Cortex-M3 (revision r2p1)  RISC Harvard architecture with 3-stage pipeline  Supports the memory protection unit (MPU) ■ Low power consumption  Standby mode, sleep mode, and module stop function ■ On-chip extended SRAM  Up to 1 Mbyte of the on-chip extended SRAM with ECC  150 MHz ■ Data transfer  DMAC: 16 channels × 2 units  DMAC for the Ethernet controller: 1 channel ■ Event link controller  Module operations can be started by event signals rather than by interrupt handlers.
 Linked operation of modules is available even while the CPU is in the sleep state.
■ Reset and power supply voltage control  Four reset sources including a pin reset  Dual power-voltage configuratio...


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