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GS88018AT-150

ETC
Part Number GS88018AT-150
Manufacturer ETC
Description 512K x 18/ 256K x 32/ 256K x 36 9Mb Sync Burst SRAMs
Published Mar 23, 2005
Detailed Description GS88018/32/36AT-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configur...
Datasheet PDF File GS88018AT-150 PDF File

GS88018AT-150
GS88018AT-150

Overview
GS88018/32/36AT-250/225/200/166/150/133 100-Pin TQFP Commercial Temp Industrial Temp Features • FT pin for user-configurable flow through or pipeline operation • Single Cycle Deselect (SCD) operation • 2.
5 V or 3.
3 V +10%/–10% core power supply • 2.
5 V or 3.
3 V I/O supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package Pipeline 3-1-1-1 3.
3 V 2.
5 V Flow Through 2-1-1-1 3.
3 V 2.
5 V tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) tKQ tCycle Curr (x18) Curr (x32/x36) Curr (x18) Curr (x32/x36) -250 -225 -200 -166 -150 -133 Unit 2.
5 2.
7 3.
0 3.
4 3.
8 4.
0 ns 4.
0 4.
4 5.
0 6.
0 6.
7 7.
5 ns 280 330 275 320 5.
5 5.
5 175 200 175 200 255 300 250 295 6.
0 6.
0 165 190 165 190 230 270 230 265 6.
5 6.
5 160 180 160 180 200 230 195 225 7.
0 7.
0 150 170 150 170 185 215 180 210 7.
5 7.
5 145 165 145 165 165 190 165 185 8.
5 8.
5 135 150 135 150 mA mA mA mA ns ns mA mA mA mA 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs 250 MHz–133 MHz 2.
5 V or 3.
3 V VDD 2.
5 V or 3.
3 V I/O cycles can be initiated with either ADSP or ADSC inputs.
In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV.
The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input.
The Burst function need not be used.
New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14).
Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register.
Holding FT high places the RAM in Pipeline mode, activating the rising-edgetriggered Data ...


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