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DM74S112

Fairchild Semiconductor
Part Number DM74S112
Manufacturer Fairchild Semiconductor
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
Published Dec 12, 2014
Detailed Description DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1...
Datasheet PDF File DM74S112 PDF File

DM74S112
DM74S112

Overview
DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised April 2000 DM74S112 Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flops on the falling edge of the clock pulse.
The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse.
Data on the J and K inputs can be changed while the clock is HIGH or LOW without affecting the outputs as long as setup and hold times are not violated.
A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Ordering Code: Order Number Package Number Package Description DM74S112 N16E 16-Lead Plastic Dual-I...


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