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AR2317

Atheros
Part Number AR2317
Manufacturer Atheros
Description Single Chip MAC/Baseband/Radio Processor
Published Dec 21, 2014
Detailed Description Data Sheet PRELIMINARY April 2006 AR2317 Single Chip MAC/Baseband/Radio and Processor for 2.4 GHz Wireless LANs Genera...
Datasheet PDF File AR2317 PDF File

AR2317
AR2317

Overview
Data Sheet PRELIMINARY April 2006 AR2317 Single Chip MAC/Baseband/Radio and Processor for 2.
4 GHz Wireless LANs General Description Features The Atheros AR2317 is an all-CMOS, fully- ■ Integrated high-output PA integrated, single-chip 802.
11b/g WLAN ■ Integrated LNA/optional external LNA solution.
It integrates the PA, LNA, 2.
4GHz support radio, baseband PHY, MAC, and a MIPS 4000 ■ Integrated 1.
8 V voltage regulator; NO need CPU into a single chip for wireless access point for a 1.
8 V supply and router applications.
Other major modules ■ Switched Rx antenna diversity include 802.
3 Ethernet MAC and MII interface, ■ Integrated Rx/Tx antenna switch SDRAM controller, external memory interface ■ Integrated power detector for Flash, ROM, or RAM, a UART, GPIOs as ■ 25 MHz output for Ethernet switch well as LED controls.
The AR2317 implements an 802.
11 MAC/BB processor supporting all IEEE 802.
11g data rates (1 to 54 Mbps) and all IEEE 802.
11b Ycomplementary key coding (CCK) data rates (1 to 11 Mbps).
Additional features include Pforward error correction coding at rates for 1/ 2, 2/3, and 3/4, signal detection, automatic Ogain control, frequency offset estimation, symbol timing, channel estimation, error Crecovery, enhanced security, and quality of service (QoS).
The AR2317 performs receive Tand transmit filtering for IEEE 802.
3 and 802.
11 networks.
DO NOSystem Block Diagram ■ Integrated MIPS 4000 processor ■ 180 MHz processor frequency ■ IEEE 802.
11b/g Access Point, Ad Hoc, and station functions supported ■ OFDM and CCK modulation schemes supported ■ Data rates of 1, 2, 5.
5, 6, 9, 11, 12, 18, 24, 36, 48, 54 Mbps ■ IEEE 802.
3 Ethernet MAC supporting 10/ 100 Mbps, full and half duplex, and MII interface to external Ethernet PHY ■ UART for console support ■ IEEE 1149.
1 standard test access port and boundary scan architecture supported ■ EJTAG based debugging of the processor core supported ■ Standard 0.
18 μm CMOS technology ■ 12 mm x 12 mm 260 BGA packag...


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