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CY7C024A

Cypress Semiconductor
Part Number CY7C024A
Manufacturer Cypress Semiconductor
Description 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM
Published Feb 8, 2015
Detailed Description CY7C024/024A/0241 CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY Features ■ True dual-...
Datasheet PDF File CY7C024A PDF File

CY7C024A
CY7C024A

Overview
CY7C024/024A/0241 CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY Features ■ True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 4K x 16 organization (CY7C024/024A[1]) ■ 4K x 18 organization (CY7C0241) ■ 8K x 16 organization (CY7C025) ■ 8K x 18 organization (CY7C0251) ■ 0.
65 micron CMOS for optimum speed and power ■ High speed access: 15 ns ■ Low operating power: ICC = 150 mA (typ) ■ Fully asynchronous operation ■ Automatic power down ■ Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flag for port-to-port communication ■ Separate upper-byte and lower-byte control ■ Pin select for Master or Slave ■ Available in 84-pin (Pb-free) PLCC, 84-pin PLCC, 100-pin (Pb-free) TQFP, and 100-pin TQFP Functional Description The CY7C024/024A/0241 and CY7C025/0251 are low power CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs.
Various arbitration schemes are included on the CY7C024/ 0241 and CY7C025/0251 to handle situations when multiple processors access the same piece of data.
Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory.
The CY7C024/ 0241 and CY7C025/0251 can be used as standalone 16 or 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static RAM.
An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic.
Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE).
Two flags are provided on each port (BUSY and INT).
BUSY...


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