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NT5CB64M16AP

Nanya
Part Number NT5CB64M16AP
Manufacturer Nanya
Description 1Gb DDR3 SDRAM A-Die
Published Feb 24, 2015
Detailed Description 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  1.5V ± 0.075V (JEDEC Standard Power Supply) ...
Datasheet PDF File NT5CB64M16AP PDF File

NT5CB64M16AP
NT5CB64M16AP


Overview
1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Feature  1.
5V ± 0.
075V (JEDEC Standard Power Supply)  8 Internal memory banks (BA0- BA2)  Differential clock input (CK, )  Programmable  Latency: 5, 6, 7, 8, 9  Programmable Additive Latency: 0, CL-1, CL-2  Programmable Sequential / Interleave Burst Type  Programmable Burst Length: 4, 8  8 bit prefetch architecture  Output Driver Impedance Control  Write Leveling  OCD Calibration  Dynamic ODT (Rtt_Nom & Rtt_WR)  Auto Self-Refresh  Self-Refresh Temperature  Partial Array Self-Refresh  RoHS Compliance  Packages: 78-Ball BGA for x4 & x8 components 96-Ball BGA for x16 components Description The 1Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 1,073,741,824 bits.
It is internally configured as an octal-bank DRAM.
The 1Gb chip is organized as 32Mbit x 4 I/O x 8, 16Mbit x 8 I/O x 8 bank or 8Mbit x 16 I/O x 8 bank device.
These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications.
The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and  falling).
All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion.
These devices operate with a single 1.
5V ± 0.
75V power supply and are available in BGA packages.
REV 1.
2 01 / 2009 1 1Gb DDR3 SDRAM A-Die NT5CB256M4AN / NT5CB128M8AN / NT5CB64M16AP Pin Configuration – 78 balls BGA Package (x4) < TOP View> See the balls through the package 1 VSS VSS VDDQ VSSQ VREFDQ NC ODT NC VSS VDD VSS VDD VSS 2 VDD VSSQ DQ2 NC VDDQ VSS VDD  BA0 A3 A5 A7  3 NC DQ0 DQS  NC    BA2 A0 A2 A9 A13 x4 7 A NC B DM C DQ1 D VDD E NC F CK G  H A10/AP J NC K A12/ L A1 M A11 N NC 8 VSS VSSQ DQ...



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