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GAL20XV10

Part Number	GAL20XV10
Manufacturer	Lattice Semiconductor
Description	High-Speed E2CMOS PLD Generic Array Logic
Published	Mar 23, 2005
Detailed Description	GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic™ Features • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 10 ns Maximum Pro...
Datasheet	GAL20XV10 PDF File

Overview

GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic™ Features • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 16 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 90mA Maximum Icc — 75mA Typical Icc • ACTIVE PULL-UPS ON ALL PINS • E2 CELL TECHNOLOGY — Reconfigurable Logic — Reprogrammable Cells — 100% Tested/100% Yields — High Speed Electrical Erasure (<100 ms) — 20 Year Data Retention • TEN OUTPUT LOGIC MACROCELLS — XOR Gate Capability on all Outputs — Full Function and Parametric Compatibility with PAL12L10, 20L10, 20X10, 20X8, 20X4 — Registered or Combinatorial with Polarity • PRELOAD AND POWER-ON RESET OF ALL REGISTERS • APPLICATIONS INCLUDE: — High Speed Counters — Graphics Processing — Comparators • ELECTRONIC SIGNATURE FOR IDENTIFICATION Functional Block Diagram I/CLK 4 OLMC I/O/Q I 4 OLMC I 4 I/O/Q I OLMC I/O/Q PROGRAMMABLE AND-ARRAY (40 X 40) 4 OLMC I I/O/Q 4 OLMC I I/O/Q I 4 OLMC I/O/Q I 4 OLMC I/O/Q I 4 OLMC I/O/Q I 4 OLMC I/O/Q I 4 OLMC I/O/Q Description The GAL20XV10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed Exclusive-OR PLD available in the market.
At 90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides a substantial savings in power when compared to bipolar counterparts.
E2CMOS technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
An important subset of the many architecture configurations possible with the GAL20XV10 are the PAL® architectures listed in the macrocell description section of this document.
The GAL20XV10 is capable of emulating these PAL architec...

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GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic - Lattice Semiconductor

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