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CY62147GE

Cypress Semiconductor
Part Number CY62147GE
Manufacturer Cypress Semiconductor
Description 4-Mbit (256K words x 16 bit) Static RAM
Published Apr 29, 2015
Detailed Description CY62147G/CY621472G CY62147GE MoBL® 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256...
Datasheet PDF File CY62147GE PDF File

CY62147GE
CY62147GE

Overview
CY62147G/CY621472G CY62147GE MoBL® 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC) Features ■ High speed: 45 ns/55 ns ■ Ultra-low standby power ❐ Typical standby current: 3.
5 A ❐ Maximum standby current: 8.
7 A ■ Embedded ECC for single-bit error correction[1, 2] ■ Wide voltage range: 1.
65 V to 2.
2 V, 2.
2 V to 3.
6 V, and 4.
5 V to 5.
5 V ■ 1.
0-V data retention ■ TTL-compatible inputs and outputs ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ Pb-free 48-ball VFBGA and 44-pin TSOP II packages Functional Description CY62147G and CY62147GE are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC.
Both devices are offered in single and dual chip enable options and in multiple pin configurations.
The CY62147GE device includes an ERR pin that signals an error-detection and correction event during a read cycle.
Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW.
Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as low and CE2 as HIGH.
Data writes are performed by asserting the Write Enable (WE) input LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location.
BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7.
Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O15).
Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a HI-Z state when the device is deselected (CE HI...


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