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ICS9UMS9610

IDT
Part Number ICS9UMS9610
Manufacturer IDT
Description PC MAIN CLOCK
Published May 7, 2015
Detailed Description PC MAIN CLOCK Recommended Application: Poulsbo Based Ultra-Mobile PC (UMPC) - CK610 Output Features: • 3 - CPU low power...
Datasheet PDF File ICS9UMS9610 PDF File

ICS9UMS9610
ICS9UMS9610

Overview
PC MAIN CLOCK Recommended Application: Poulsbo Based Ultra-Mobile PC (UMPC) - CK610 Output Features: • 3 - CPU low power differential push-pull pairss • 3 - SRC low power differential push-pull pairs • 1 - LCD100 SSCD low power differential push-pull pair • 1 - DOT96 low power differential push-pull pair • 1 - REF, 14.
31818MHz, 3.
3V SE output Pin Configuration Advance Information ICS9UMS9610 Features/Benefits: • Supports Dothan ULV CPUs with 100 to 200 MHz CPU outputs • Dedicated TEST/SEL and TEST/MODE pins saves isolation resistors on pins • CPU STOP# input for power manangment • Fully integrated Vreg • Integrated series resistors on differential outputs • 1.
5V VDD IO, 1.
5V VDD core, 3.
3V VDD supply pin for REF CPUT0_LPR CPUC0_LPR VDDIO_1.
5 GNDCPU CPUT1_LPR CPUC1_LPR VDDCORE_1.
5 VDDIO_1.
5 GNDCPU CPUT2_LPR CPUC2_LPR FSB_L_1.
5 48 47 46 45 44 43 42 41 40 39 38 37 CPU_STOP#_3.
3 1 36 *CR#2_1.
5 CLKPWRGD#/PD_3.
3 2 35 SRCT2_LPR X2 3 34 SRCC2_LPR X1 4 33 GNDSRC VDDREF_3.
3 5 32 SRCT1_LPR REF_3.
3_2x 6 GNDREF 7 9UMS9610 31 SRCC1_LPR 30 VDDIO_1.
5 VDDCORE_1.
5 8 29 VDDCORE_1.
5 FSC_L_1.
5 9 28 *CR#1_1.
5 TEST_MODE_1.
5 10 27 SRCT0_LPR TEST_SEL_1.
5 11 26 SRCC0_LPR SCLK_3.
3 12 25 GNDSRC 13 14 15 16 17 18 19 20 21 22 23 24 SDATA_3.
3 VDDCORE_1.
5 VDDIO_1.
5 DOT96C_LPR DOT96T_LPR GNDDOT GNDLCD LCD100C_LPR LCD100T_LPR VDDIO_1.
5 VDDCORE_1.
5 *CR#0_1.
5 IDTTM/ICSTM PC MAIN CLOCK 48-pin MLF, 6x6 mm, 0.
4mm pitch * indicates inputs with internal pull up of ~10Kohm to 1.
5V 1 1336—07/21/08 ICS9UMS9610 PC MAIN CLOCK Advance Information Pin Description PIN # PIN NAME TYPE DESCRIPTION 1 CPU_STOP#_3.
3 IN This active-low input stops all CPU clocks that are set to be stoppable.
This level sensitive strobe determines when latch inputs are valid and are 2 CLKPWRGD#/PD_3.
3 IN ready to be sampled.
When high, this asynchronous input places the device into the power down state.
3 X2 OUT Crystal output, Nominally 14.
318MHz 4 X1 IN Crystal input, Nominally 14.
318MHz.
...


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