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TC75W59FK

Toshiba
Part Number TC75W59FK
Manufacturer Toshiba
Description Dual Comparator
Published May 12, 2015
Detailed Description TC75W59FU/FK TOSHIBA CMOS Linear Integrated Circuit Silicon Monolithic TC75W59FU, TC75W59FK Dual Comparator TC75W59 is a...
Datasheet PDF File TC75W59FK PDF File

TC75W59FK
TC75W59FK

Overview
TC75W59FU/FK TOSHIBA CMOS Linear Integrated Circuit Silicon Monolithic TC75W59FU, TC75W59FK Dual Comparator TC75W59 is a CMOS type general-purpose dual comparator capable of single power supply operation and using lower supply currents than the conventional bipolar comparators.
Its open drain output forms wired OR with other open drain outputs.
Features z Low supply current: IDD = 200μA (typ.
) z Single power supply operation z Wide common mode input voltage range: VSS to VDD−0.
9V z Open drain output circuit z Low input bias current z Small package Marking (Top View) Weight SSOP8-P-0.
65: 0.
021g (typ.
) SSOP8-P-0.
50A: 0.
01g (typ.
) Pin Connection (Top View) Start of commercial production 1997-05 1 2014-03-01 Absolute Maximum Ratings (Ta = 25°C) TC75W59FU/FK Characteristic Symbol Rating N Supply voltage Differential input voltage Input voltage Output current Power dissipation Operating temperature Storage temperature VDD, VSS ±3.
5 or 7 V DVIN ±7 V VIN VSS to VDD V IO ±35 mA 250 (TC75W59FU) PD mW 200 (TC75W59FK) Topr −40 to 85 °C Tstg −55 to 125 °C Note: Using continuously under heavy loads (e.
g.
the application of high temperature/current/voltage and the significant change in temperature, etc.
) may cause this product to decrease in the reliability significantly even if the operating conditions (i.
e.
operating temperature/current/voltage, etc.
) are within the absolute maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.
e.
reliability test report and estimated failure rate, etc).
Note: Since this product sometimes brings about latchcap, which is peculiar to CMOS devices, note the following points: • Don’t raise the voltage level of I/O pins beyond VDD, nor lower it below VSS.
Consider the timing for power supply, too.
• Don’t let any abnormal noise enter ...


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