DatasheetsPDF.com

PLL52C61-23

PhaseLink
Part Number PLL52C61-23
Manufacturer PhaseLink
Description Pentium/SDRAM Clock Generator
Published Jul 24, 2015
Detailed Description PLL52C61-23 Pentium/SDRAM Clock Generator for 2-DIMM FEATURES n Generates all clock frequencies for Pentium, AMD and Cy...
Datasheet PDF File PLL52C61-23 PDF File

PLL52C61-23
PLL52C61-23


Overview
PLL52C61-23 Pentium/SDRAM Clock Generator for 2-DIMM FEATURES n Generates all clock frequencies for Pentium, AMD and Cyrix system requiring multiple CPU clocks (SDRAM, Shared memory architecture).
n Supports up to12 Synchronous CPU clocks.
n 6 PCI BUS clocks selectable between synchronous and asynchronous mode.
n One 14.
318Mhz reference clock n One 24Mhz floppy clock and one 48Mhz USB clock.
n Proven power-on strapping techniques to minimize four input pins.
In any cases, no glitches will be produced from the output pins during power on.
n 3.
3V and 5V operation.
n Available in 300mil 32 pin SOJ.
DESCRIPTION The PLL52C61-23 is a high performance system clock generator designed to support INTEL 430VX/TX PCIset motherboard with up to 2 DIMM Pentium based systems.
All output clocks skew and jitter performance are designed to be fully compliant with INTEL Pentium CPU timing requirements.
TIMING SPECIFICATIONS PCLK-PCLK skew PCLK-BCLK skew PCLK,BCLK slew rate PCLK Jitter <250 ps 1~5 ns (PCLK leads) > 1 V/ns (0.
4 ~2.
4V) ±200 ps cycle-cycle BLOCK DIAGRAM PIN INFORMATION FREQUENCY SELECTION (MHz) F2 F1 F0 PCLK (0:11) BCLK(0:5) PCI=1 PCI=0 0 0 0 50 25 32 0 0 1 60 30 32 0 1 0 66.
6 33.
3 32 0 1 1 Test Test Test 100 33 16.
5 32 101 75 37.
5 32 1 1 0 83.
3 41.
7 32 1 1 1 68.
4 34.
2 32 Note: F2,F1,F0 and PCI are selectable only during Power-on.
They are HIGH by default and Low when 10K Ω pull-down is attached.
45437 Warm Springs Blvd.
, Fremont, CALIFORNIA, TEL 510-492-0990 FAX 510-492-0991 9708.
Rev.
1A Page 1 ...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)