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STM8S007C8

STMicroelectronics
Part Number STM8S007C8
Manufacturer STMicroelectronics
Description 24 MHz STM8S 8-bit MCU
Published Aug 17, 2015
Detailed Description STM8S007C8 Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash, true data EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C...
Datasheet PDF File STM8S007C8 PDF File

STM8S007C8
STM8S007C8

Overview
STM8S007C8 Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash, true data EEPROM, 10-bit ADC, timers, 2 UARTs, SPI, I²C Datasheet - production data Features  Core – Max fCPU: up to 24 MHz, 0 wait states @ fCPU 16 MHz – Advanced STM8 core with Harvard architecture and 3-stage pipeline – Extended instruction set – Max 20 MIPS @ 24 MHz  Memories – Program: 64 Kbytes Flash; data retention 20 years at 55 °C after 100 cycles – Data: 128 bytes true data EEPROM; endurance 100 kcycles – RAM: 6 Kbytes  Clock, reset and supply management – 2.
95 to 5.
5 V operating voltage – Low power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low power 128 kHz RC – Clock security system with clock monitor – Wait, active-halt, & halt low power modes – Peripheral clocks switched off individually – Permanently active, low consumption power-on and power-down reset  Interrupt management – Nested interrupt controller with 32 interrupts – Up to 37 external interrupts on 6 vectors  Timers – 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) – Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization – 8-bit basic timer with 8-bit prescaler – Auto wakeup timer – Window watchdog, independent watchdog LQFP48 7 x 7mm  Communications interfaces – UART with clock output for synchronous operation - LIN master mode – UART with LIN 2.
1 compliant, master/slave modes and automatic resynchronization – SPI interface up to 10 Mbit/s – I2C interface up to 400 Kbit/s  10-bit ADC with up to 16 channels  I/Os – 38 I/Os including 16 high sink outputs – Highly robust I/O design, immune against current injection – Development support – Single wire interface module (SWIM) and debug module (DM) March 2015 This is information on a product in full production.
DocID022171 Rev 5 1/92 www.
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