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NB7L1008

ON Semiconductor
Part Number NB7L1008
Manufacturer ON Semiconductor
Description 2.5V / 3.3V 1:8 LVPECL Fanout Buffer
Published Sep 1, 2015
Detailed Description NB7L1008 2.5V / 3.3V 1:8 LVPECL Fanout Buffer Multi−Level Inputs w/ Internal Termination Description The NB7L1008 is a h...
Datasheet PDF File NB7L1008 PDF File

NB7L1008
NB7L1008

Overview
NB7L1008 2.
5V / 3.
3V 1:8 LVPECL Fanout Buffer Multi−Level Inputs w/ Internal Termination Description The NB7L1008 is a high performance differential 1:8 Clock/Data fanout buffer.
The NB7L1008 produces eight identical output copies of Clock or Data operating up to 7 GHz or 12 Gb/s, respectively.
As such, the NB7L1008 is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications.
The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin.
This feature allows the NB7L1008 to accept various logic standards, such as LVPECL, CML, LVDS logic levels.
The VREFAC reference output can be used to rebias capacitor−coupled differential or single−ended input signals.
The 1:8 fanout design was optimized for low output skew applications.
The NB7L1008 is a member of the GigaComm™ family of high performance clock products.
Features • Typical Maximum Input Data Rate > 12 Gb/s Typical • Data Dependent Jitter < 15 ps • Maximum Input Clock Frequency > 7 GHz Typical • Random Clock Jitter < 0.
8 ps RMS • Low Skew 1:8 LVPECL Outputs, < 20 ps max • Multi−Level Inputs, accepts LVPECL, CML, LVDS • 160 ps Typical Propagation Delay • 50 ps Typical Rise and Fall Times • Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical • Operating Range: VCC = 2.
375 V to 3.
6 V, GND = 0 V • Internal Input Termination Resistors, 50 W • VREFAC Reference Output • QFN−32 Package, 5 mm x 5 mm • −40°C to +85°C Ambient Operating Temperature • These are Pb−Free and Halide−Free Devices http://onsemi.
com MARKING 32 DIAGRAM 1 32 QFN32 MN SUFFIX CASE 488AM 1 NB7L 1008 AWLYYWWG G A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) SIMPLIFIED LOGIC DIAGRAM Q0 Q0 Q1 Q1 Q2 Q2 IN 50W VT 50W IN VREFAC Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 © Semiconductor Components Industries, LLC, 2014 April, 2014 − Rev.
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