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AVR200856

A-LINK
Part Number AVR200856
Manufacturer A-LINK
Description DDR2 SDRAM
Published Oct 22, 2015
Detailed Description DDR2 SDRAM AVR201628 (128M X 16 ) AVR200856 (256M X 8 ) AVR200412 (512M X 4 ) Features • VDD = +1.8V ±0.1V, VDDQ = +1.8...
Datasheet PDF File AVR200856 PDF File

AVR200856
AVR200856

Overview
DDR2 SDRAM AVR201628 (128M X 16 ) AVR200856 (256M X 8 ) AVR200412 (512M X 4 ) Features • VDD = +1.
8V ±0.
1V, VDDQ = +1.
8V ±0.
1V • JEDEC-standard 1.
8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Duplicate output strobe (RDQS) option for x8 • DLL to align DQ and DQS transitions with CK • 8 internal banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8192-cycle refresh • On-die termination (ODT) • Industrial temperature (IT) option • RoHS-compliant • Supports JEDEC clock jitter specification Table 1: Key Timing Parameters Options1 Marking • Configuration – 512 Meg x 4 (64 Meg x 4 x 8 banks) 512M4 – 256 Meg x 8 (32 Meg x 8 x 8 banks) 256M8 – 128 Meg x 16 (16 Meg x 16 x 8 banks) 128M16 • FBGA package (Pb-free) – x16 – 84-ball FBGA (11.
5mm x 14mm) Rev.
A ...


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