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MB9BF322M

Fujitsu
Part Number MB9BF322M
Manufacturer Fujitsu
Description 32-bit ARM Microcontroller
Published Nov 11, 2015
Detailed Description FUJITSU SEMICONDUCTOR DATA SHEET DS706-00049-1v0-E 32-bit ARMTM CortexTM-M3 based Microcontroller MB9B320M Series MB9...
Datasheet PDF File MB9BF322M PDF File

MB9BF322M
MB9BF322M


Overview
FUJITSU SEMICONDUCTOR DATA SHEET DS706-00049-1v0-E 32-bit ARMTM CortexTM-M3 based Microcontroller MB9B320M Series MB9BF324K/L/M, MB9BF322K/L/M, MB9BF321K/L/M  DESCRIPTION The MB9B320M Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have peripheral functions such as various timers, ADCs, DACs and Communication Interfaces (USB, UART, CSIO, I2C, LIN).
The products which are described in this data sheet are placed into TYPE9 product categories in "FM3 Family PERIPHERAL MANUAL".
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Copyright©2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved 2012.
12 MB9B320M Series  FEATURES  32-bit ARM Cortex-M3 Core  Processor version: r2p1  Up to 72 MHz Frequency Operation  Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 48 peripheral interrupts and 16 priority levels  24-bit System timer (Sys Tick): System timer for OS task management  On-chip Memories [Flash memory]  Dual operation Flash memory  Main area: Up to 256 Kbytes  Work area: 32 Kbytes  Read cycle: 0 wait-cycle  Security function for code protection [SRAM] This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1).
SRAM0 is connected to I-code bus or D-code bus of Cortex-M3 core.
SRAM1 is connected to System bus.
 SRAM0: Up to 16 Kbytes  SRAM1: Up to 16 Kbytes  USB Interface The USB interface is composed of Function and Host.
[USB function]  USB2.
0 Full-Speed supported  Max 6 EndPoint supported  EndPoint 0 is control transfer  EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer  EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer  EndPoint 1 to 5 are comprised of Double Buffers.
[USB host]  USB2.
0 Full/Low-speed supported  Bu...


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