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EM44DM0888LBA

Part Number	EM44DM0888LBA
Manufacturer	Eorex
Description	Double DATA RATE SDRAM
Published	Jan 23, 2016
Detailed Description	Revision History Revision 0.1 (Feb. 2011) -First release. Revision 0.2 (Jan.2013) -Add speed 1066. EM44DM0888LBA Feb. ...
Datasheet	EM44DM0888LBA PDF File

Overview

Revision History Revision 0.
1 (Feb.
2011) -First release.
Revision 0.
2 (Jan.
2013) -Add speed 1066.
EM44DM0888LBA Feb.
2012 1/29 www.
eorex.
com EM44DM0888LBA 1Gb (16M×8Bank×8) Double DATA RATE 2 SDRAM Features • JEDEC Standard VDD/VDDQ = 1.
8V±0.
1V.
• All inputs and outputs are compatible with SSTL_18 interface.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks • Posted CAS • Bust length: 4 and 8.
• Programmable CAS Latency (CL): 6 & 7 • Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5 & 6.
• Write Latency (WL) =Read Latency (RL) -1.
• Read Data Strobe (RDQS) supported • Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition with CK transition.
• DM mask write data-in at the both rising and falling edges of the data strobe.
• Sequential & Interleaved Burst type available.
• Off-Chip Driver (OCD) Impedance Adjustment • On Die Termination (ODT) • Auto Refresh and Self Refresh • 8,192 Refresh Cycles / 64ms • 7.
8us at average periodic refresh interval • RoHS Compliance • tRAS lockout supported • High Temperature Self-Refresh rate enable Description The EM44DM0888LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 1,073,741,824 bits which organized as 16Mbits x 8 banks by 8 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 1066 MT/sec (DDR2-1066) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK...

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EM44DM0888LBA Double DATA RATE SDRAM - Eorex

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