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HEF4001B

Philips
Part Number HEF4001B
Manufacturer Philips
Description Quadruple 2-input NOR gate
Published Jan 28, 2016
Detailed Description INTEGRATED CIRCUITS DATA SHEET www.DataSheet4U.com For a complete data sheet, please also download: • The IC04 LOCMOS HE...
Datasheet PDF File HEF4001B PDF File

HEF4001B
HEF4001B

Overview
INTEGRATED CIRCUITS DATA SHEET www.
DataSheet4U.
com For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4001B gates Quadruple 2-input NOR gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Quadruple 2-input NOR gate DESCRIPTION The HEF4001B provides the positive quadruple 2-input NOR function.
The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.
www.
DataSheet4U.
com Product specification HEF4001B gates Fig.
2 Pinning diagram.
Fig.
1 Functional diagram.
HEF4001BP(N): 14-lead DIL; plastic (SOT27-1) HEF4001BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4001BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.
3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Quadruple 2-input NOR gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP MAX Propagation delays In → On www.
DataSheet4U.
coHmIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 5 60 120 10 tPHL 25 50 15 20 40 5 50 100 10 tPLH 25 45 15 20 35 5 60 120 10 tTHL 30 60 15 20 40 5 60 120 10 tTLH 30 60 15 20 40 Product specification HEF4001B gates TYPICAL EXTRAPOLATION FORMULA ns 33 ns + (0,55 ns/pF) CL ns 14 ns + (0,23 ns/pF) CL ns 12 ns + (0,16 ns/pF) CL ns 23 ns + (0,55 ns/pF) CL ns 14 ns + (0,23 ns/pF) CL ns 12 ns + (0,16 ns/pF) CL ns 10 ns + (1,0 ns/pF) CL ns 9 ns + (0,42 ns/pF) CL ns 6 ns + (0,28 ns/pF) CL ns 10 ns + (1,0 ns/pF) CL ns 9 ns + (0,42 ns/pF) CL ns 6 ns + (0,28 ns/pF) CL Dynamic power dissipation per package (P) VDD V TYPICAL FORMULA FOR P (µW) 5 1100 fi + ∑ (foCL) × VDD2 where 10 5000 fi + ∑ (foCL) × VDD2 fi = input freq.
(MHz) 15 14 200 fi + ∑ (foCL) × VDD2 fo = output fr...


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