DatasheetsPDF.com

SI53304

Part Number	SI53304
Manufacturer	Silicon Laboratories
Description	1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR
Published	Mar 4, 2016
Detailed Description	Si53304 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE Features  6 differenti...
Datasheet	SI53304 PDF File

Overview

Si53304 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE Features  6 differential or 12 LVCMOS outputs  Independent VDD and VDDO:  Ultra-low additive jitter: 45 fs rms 1.
8/2.
5/3.
3 V  Wide frequency range: 1 to 725 MHz  1.
2/1.
5 V LVCMOS output support  Any-format input with pin selectable  Excellent power supply noise output formats: LVPECL, Low Power rejection (PSRR) LVPECL, LVDS, CML, HCSL,  Selectable LVCMOS drive strength to LVCMOS tailor jitter and EMI performance  2:1 mux with hot-swappable inputs  Small size: 32-QFN (5x5 mm)  Glitchless input clock switching  RoHS compliant, Pb-free  Synchronous output enable  Industrial temperature range:  Individual output enable –40 to +85 °C Applications  High-speed clock distribution  Ethernet switch/router  Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Description The Si53304 is an ultra low jitter six output differential buffer with pin-selectable output clock signal format and individual OE.
The Si53304 features a 2:1 mux with glitchless switching, making it ideal for redundant clocking applications.
The Si53304 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53304 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation without the need for external circuitry.
Functional Block Diagram VREF Vref Generator VDD Power Supply Filtering VDDOA SFOUTA[1:0] OE[2:0] Ordering Information: See page 28.
Pin Assignments Si53304 25 26 27 28 29 30 31 32 OE0 SFOUTA[1] SFOUTA[0] Q0 Q0 GND VDD CLK_SEL 1 2 3 4 5 6 7 8 GND PAD 24 OE5 23 SFOUTB[1] 22 SFOUTB[0] 21 Q5...

Similar Datasheet

SI533 DUAL FREQUENCY CRYSTAL OSCILLATOR - Silicon Laboratories
SI5330 LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR - Silicon Laboratories
Si53301 Ultra-Low Additive Jitter Fanout Clock Buffers - Skyworks
SI53301 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR - Silicon Laboratories
Si53302 Ultra-Low Additive Jitter Fanout Clock Buffers - Skyworks
SI53302 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR - Silicon Laboratories
Si53303 Ultra-Low Additive Jitter Fanout Clock Buffers - Skyworks
SI53303 DUAL 1:5 LOW JITTER BUFFER/LEVEL TRANSLATOR - Silicon Laboratories
Si53304 Ultra-Low Additive Jitter Fanout Clock Buffers - Skyworks
SI53304 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR - Silicon Laboratories

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)