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SI53308

Part Number	SI53308
Manufacturer	Silicon Laboratories
Description	DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR
Published	Mar 4, 2016
Detailed Description	Si53308 DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR Features  6 differential or 12 (in phase)  Loss of signal (LOS...
Datasheet	SI53308 PDF File

Overview

Si53308 DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR Features  6 differential or 12 (in phase)  Loss of signal (LOS) monitors for LVCMOS outputs loss of input clock  Ultra-low additive jitter: 45 fs rms  Independent VDD and VDDO :  Wide frequency range: 1 to 725 MHz 1.
8/2.
5/3.
3 V  Any-format input with pin selectable  Selectable LVCMOS drive strength to output formats: LVPECL, low power tailor jitter and EMI performance LVPECL, LVDS, CML, HCSL, LVCMOS  Synchronous output enable  Output clock division: /1, /2, /4  Low output-output skew: 25 ps  Small size: 32-QFN (5 mm x 5 mm)  RoHS compliant, Pb-free  Industrial temperature range: –40 to +85 °C Applications  High-speed clock distribution  Ethernet switch/router  Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Description The Si53308 is an ultra low jitter six output differential buffer with pin-selectable output clock signal format and divider selection.
The device is a dual 1:3 buffer providing the functionality of two independent buffers in a single IC.
The Si53308 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability.
The Si53308 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation without the need for external circuitry.
Functional Block Diagram LOS0 9 Q1 CLK0 10 Q1 CLK0 11 Q2 OEA 12 Q2 OEB 13 Q3 CLK1 14 Q3 CLK1 15 Q4 LOS1 16 Q4 Ordering Information: See page 28.
Pin Assignments Si53308 25 26 27 28 29 30 31 32 DIVA 1 SFOUTA[1] 2 SFOUTA[0] 3 Q0 4 Q0 5 GND 6 VDD 7 NC 8 GND PAD 24 DIVB 23 SFOUTB[1] 22 SFOUTB[0] 21 Q5 20 Q5 19 VDDOB 18 VDDOA 17 VREF Patents pending VREF CLK0 CLK0 Vref Generator Power S...

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