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SL16010DC

Part Number	SL16010DC
Manufacturer	Silicon Laboratories
Description	Low Jitter and Power Clock Generator
Published	Mar 4, 2016
Detailed Description	SL16010DC Low Jitter and Power Clock Generator with SSCG Key Features • Low power dissipation - 13.5mA-typ CL=15pF - 1...
Datasheet	SL16010DC PDF File

Overview

SL16010DC Low Jitter and Power Clock Generator with SSCG Key Features • Low power dissipation - 13.
5mA-typ CL=15pF - 18.
0mA-max CL=15pF • 3.
3V +/-10% power supply range • 27.
000MHz crystal or clock input • 27.
000MHz REFCLK • 100MHz SSCLK with SSEL0/1 spread options • Low CCJ Jitter • Low LT Jitter • Internal Voltage Regulators • 45% to 55% Output Duty Cycle • On-chip Crystal Oscillator • -10 to +85 Temperature Range • 10-pin 3x3x0.
75 mm TDFN package Application • Video Cards • NB and DT PCs • HDTV and DVD-R/W • Routers, Switches and Servers • Data Communications • Embeded Digital Applications Block Diagram Description The SL16010DC is a low power dissipation spread spectrum clock generator using SLI proprietary low jitter PLL.
The SL16010DC provides two output clocks.
REFCLK (Pin-9) which is a buffered output of the 27.
000MHz input crystal and SSCLK (Pin-5) which is synthesized as 100.
000MHz nominal by an internal PLL using the 27.
00MHz external input crystal or clock.
In addition, SSEL0 (Pin-7) and SSEL1 (Pin-3) spread percent selection control inputs enable users to select from 0.
0% (no spread) to -3.
0% down spread at 100.
000MHz SSCLK output to reduce and optimize system EMI levels.
The SL16010DC operates in an extended temperature range of -10 to +85°C.
Contact SLI for other programmable frequencies, Spread Spectrum Clock (SSC) options, as well as 2.
5V+/-10 and 1.
8V+/-5% power supply options.
Benefits • EMI Reduction • Improved Jitter • Low Power Dissipation • Eleminates external Xtals or XOs XIN/CLKIN 1 XOUT 10 300K Low Jitter PLL With Modulation Control Input Decoder 46 VDD1 VSS1 82 VDD2 VSS2 7 SSEL0 3 SSEL1 Figure 1.
Block Diagram 9 REFCLK 27.
000MHz 5 SSCLK 100.
000MHz Rev 2.
6, August 1, 2010 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 Page 1 of 8 www.
silabs.
com Pin Configuration SL16010DC XIN/CLKIN 1 VSS2 2 SSEL1 VDD1 3 4 SSCLK 5 10 XOUT 9 REFCLK 8 VDD2 7 SSEL0 6 VSS1 Figure 2.
10-Pin TDFN (3x3x0.
75 mm)...

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SL16010DC Low Jitter and Power Clock Generator - Silicon Laboratories

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