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M24C32-A125

STMicroelectronics
Part Number M24C32-A125
Manufacturer STMicroelectronics
Description Automotive 32-Kbit serial I2C bus EEPROM
Published Mar 17, 2016
Detailed Description M24C32-A125 Datasheet Automotive 32-Kbit serial I²C bus EEPROM with 1 MHz clock TSSOP8 169 mil width SO8N (MN) 150 mil...
Datasheet PDF File M24C32-A125 PDF File

M24C32-A125
M24C32-A125


Overview
M24C32-A125 Datasheet Automotive 32-Kbit serial I²C bus EEPROM with 1 MHz clock TSSOP8 169 mil width SO8N (MN) 150 mil width WFDFPN8 (MF) DFN8 2 x 3 mm Product status link M24C32-A125 Features • AEC-Q100 qualified • Compatible with all I2C bus modes – 1 MHz – 400 kHz – 100 kHz • Memory array – 32 Kbit (4 Kbyte) of EEPROM – Page size: 32 byte – Additional write lockable page (identification page) • Extended temperature and voltage ranges – -40 °C to 125 °C; 1.
7 V to 5.
5 V • Schmitt trigger inputs for noise filtering.
• Short write cycle time – Byte write within 4 ms – Page write within 4 ms • Write cycle endurance – 4 million write cycles at 25 °C – 1.
2 million write cycles at 85 °C – 600 k write cycles at 125 °C • Data retention – 50 years at 125 °C – 100 years at 25 °C • ESD protection (human body model) – 4000 V • Packages – RoHS compliant and halogen-free (ECOPACK2 ) DS9133 - Rev 8 - June 2022 For further information contact your local STMicroelectronics sales office.
www.
st.
com M24C32-A125 Description 1 Description The M24C32-A125 is a 32-Kbit serial EEPROM automotive grade device operating up to 125 °C.
The M24C32A125 is compliant with the very high level of reliability defined by the automotive standard AEC-Q100 grade 1.
The device is accessed by a simple serial I2C compatible interface running up to 1 MHz.
The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory).
The M24C32-A125 is byte-alterable memories (4096 K × 8 bits) organized as 128 pages of 32 byte in which the data integrity is significantly improved with an embedded error correction code logic.
The M24C32-A125 offers an additional identification page (32 byte) in which the ST device identification can be read.
This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode.
Figure 1.
Logic diagram DATA REGISTER + ECC SENSE AMPLIFIERS PAGE LATCHES X DECODER SCL Y DECODER SDA I...



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