DatasheetsPDF.com

M5M5T5636GP-25

Mitsubishi
Part Number M5M5T5636GP-25
Manufacturer Mitsubishi
Description 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
Published Mar 31, 2016
Detailed Description January 31, 2003 Rev.0.6 Preliminary Notice: This is not final specification. Some parametric limits are subject to chan...
Datasheet PDF File M5M5T5636GP-25 PDF File

M5M5T5636GP-25
M5M5T5636GP-25

Overview
January 31, 2003 Rev.
0.
6 Preliminary Notice: This is not final specification.
Some parametric limits are subject to change.
DESCRIPTION The M5M5T5636GP is a family of 18M bit synchronous SRAMs organized as 524288-words by 36-bit.
It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.
Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability.
M5M5T5636GP operates on 2.
5V power/ 1.
8V I/O supply or a single 2.
5V power supply and are 2.
5V CMOS compatible.
FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225 and 200 MHz • Fast access time: 2.
6, 2.
8 and 3.
2 ns • Single 2.
5V -5% and +5% power supply VDD • Separate VDDQ for 2.
5V or 1.
8V I/O • Individual byte write (BWa# - BWd#) controls may be tied LOW • Single Read/Write control pin (W#) • CKE# pin to enable clock and suspend operations • Internally self-timed, registers outputs eliminate the need to control G# • Snooze mode (ZZ) for power down • Linear or Interleaved Burst Modes • Three chip enables for simple depth expansion MITSUBISHI LSIs M5M5T5636GP –25,22,20 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM APPLICATION High-end networking products that require high bandwidth, such as switches and routers.
FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV), Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#, BWd#) and Read/Write (W#).
Write operations are controlled by the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#) inputs.
All writes are conducted with on-chip synchronous self-timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK) and Snooze Enable (ZZ).
The HIGH input of ZZ pin puts the SRAM in the power-down state.
The Linear ...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)