MOSFET. FDMC86570LET60 Datasheet

FDMC86570LET60 Datasheet PDF, Equivalent


Part Number

FDMC86570LET60

Description

MOSFET

Manufacture

Fairchild Semiconductor

Total Page 7 Pages
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FDMC86570LET60 Datasheet
January 2015
FDMC86570LET60
N-Channel Shielded Gate PowerTrench® MOSFET
60 V, 87 A, 4.3 mΩ
Features
„ Extended TJ rating to 175°C
„ Shielded Gate MOSFET Technology
„ Max rDS(on) = 4.3 mΩ at VGS = 10 V, ID = 18 A
„ Max rDS(on) = 6.5 mΩ at VGS = 4.5 V, ID = 15 A
„ High performance technology for extremely low rDS(on)
„ Termination is Lead-free
„ RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Application
„ DC-DC Conversion
„
Pin 1
Pin 1
SS
SG
S
S
D
D
D
DD
D
SD
GD
Top PPoowweerr 3333 Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
ID
EAS
PD
TJ, TSTG
Parameter
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-Continuous
-Continuous
-Continuous
-Pulsed
TC = 25 °C
TC = 100 °C
TA = 25 °C
Single Pulse Avalanche Energy
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
Operating and Storage Junction Temperature Range
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
Package Marking and Ordering Information
(Note 5)
(Note 5)
(Note 1a)
(Note 4)
(Note 3)
(Note 1a)
(Note 1)
(Note 1a)
Ratings
60
±20
87
62
18
436
253
65
2.8
-55 to +175
2.3
53
Units
V
V
A
mJ
W
°C
°C/W
Device Marking
FDMC86570LT
Device
FDMC86570LET60
Package
Power33
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
©2015 Fairchild Semiconductor Corporation
FDMC86570LET60 Rev. C2
1
www.fairchildsemi.com

FDMC86570LET60 Datasheet
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
ΔBVDSS
ΔTJ
IDSS
IGSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = 250 μA, VGS = 0 V
ID = 250 μA, referenced to 25 °C
VDS = 48 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
60 V
30 mV/°C
1
±100
μA
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
1.0 1.8 3.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
-7 mV/°C
VGS = 10 V, ID = 18 A
3.1 4.3
rDS(on)
Static Drain to Source On Resistance
VGS = 4.5 V, ID = 15 A
4.7 6.5 mΩ
VGS = 10 V, ID = 18 A, TJ = 125 °C
5.0 6.9
gFS Forward Transconductance
VDD = 5 V, ID = 18 A
75 S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
VDS = 30 V, VGS = 0 V,
f = 1 MHz
4790
821
19
0.1 0.9 2.7
pF
pF
pF
Ω
Switching Characteristics
td(on)
tr
td(off)
tf
Qg(TOT)
Qg(TOT)
Qgs
Qgd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VDD = 30 V, ID = 18 A,
VGS = 10 V, RGEN = 6 Ω
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V VDD = 30 V,
ID = 18 A
19 34 ns
6.2 12 ns
38 61 ns
3.9 10 ns
63 88 nC
29 41 nC
14 nC
6.3 nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
VGS = 0 V, IS = 18 A
VGS = 0 V, IS = 1.9 A
(Note 2)
(Note 2)
trr Reverse Recovery Time
Qrr Reverse Recovery Charge
IF = 18 A, di/dt = 100 A/μs
0.8 1.3
0.7 1.2
43 69
26 42
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design.
V
V
ns
nC
a. 53 °C/W when mounted on a
1 in2 pad of 2 oz copper
b. 125 °C/W when mounted on
a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 253 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 13 A, VDD = 60 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 43 A.
4. Pulsed Id please refer to Fig 11 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMC86570LET60 Rev. C2
2
www.fairchildsemi.com


Features Datasheet pdf FDMC86570LET60 N-Channel Shielded Gate P owerTrench® MOSFET January 2015 FDMC 86570LET60 N-Channel Shielded Gate Powe rTrench® MOSFET 60 V, 87 A, 4.3 mΩ F eatures „ Extended TJ rating to 175°C „ Shielded Gate MOSFET Technology „ Max rDS(on) = 4.3 mΩ at VGS = 10 V, ID = 18 A „ Max rDS(on) = 6.5 mΩ at VGS = 4.5 V, ID = 15 A „ High performance technology for extremely low rDS(on) Termination is Lead-free „ RoHS Comp liant General Description This N-Chann el MOSFET is produced using Fairchild S emiconductor’s advanced PowerTrench® process that incorporates Shielded Gat e technology. This process has been opt imized for the on-state resistance and yet maintain superior switching perform ance. Application „ DC-DC Conversion Pin 1 Pin 1 SS SG S S D D D DD D SD GD Top PPoowweerr 3333 Bottom M OSFET Maximum Ratings TA = 25 °C unles s otherwise noted Symbol VDS VGS ID EA S PD TJ, TSTG Parameter Drain to Sour ce Voltage Gate to Source Voltage Drain Current -Continuous .
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