LVDS Isolators. ADN4651 Datasheet

ADN4651 Isolators. Datasheet pdf. Equivalent

ADN4651 Datasheet
Recommendation ADN4651 Datasheet
Part ADN4651
Description Dual-Channel LVDS Isolators
Feature ADN4651; Data Sheet 5 kV RMS/3.75 kV RMS, 600 Mbps, Dual-Channel LVDS Isolators ADN4650/ADN4651/ADN4652 136.
Manufacture Analog Devices
Datasheet
Download ADN4651 Datasheet




Analog Devices ADN4651
Data Sheet
5 kV RMS/3.75 kV RMS, 600 Mbps,
Dual-Channel LVDS Isolators
ADN4650/ADN4651/ADN4652
FEATURES
5 kV rms/3.75 kV rms LVDS isolator
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Up to 600 Mbps switching with low jitter
4.5 ns maximum propagation delay
151 ps maximum peak-to-peak total jitter at 600 Mbps
100 ps maximum pulse skew
600 ps maximum part to part skew
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection and glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN55022 Class B radiated emissions limits with
600 Mbps PRBS
Safety and regulatory approvals (20-lead SOIC package)
UL: 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 V peak
Fail-safe output high for open, short, and terminated input
conditions (ADN4651/ADN4652)
Operating temperature range: −40°C to +125°C
Choice of package and isolation options
3.75 kV rms in highly integrated 20-lead SSOP
5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance
APPLICATIONS
Analog front-end (AFE) isolation
Data plane isolation
Isolated high speed clock and data links
Isolated serial peripheral interface (SPI) over LVDS
GENERAL DESCRIPTION
The ADN4650/ADN4651/ADN46521 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 600 Mbps with very low jitter.
The devices integrate Analog Devices, Inc., iCoupler® technology,
enhanced for high speed operation, to provide galvanic isolation of
the TIA/EIA-644-A compliant LVDS drivers and receivers.
This technology allows drop-in isolation of an LVDS signal
chain.
Multiple channel configurations are offered, and the LVDS receivers
on the ADN4651/ADN4652 include a fail-safe mechanism to
FUNCTIONAL BLOCK DIAGRAMS
VIN1
VIN2
ADN4650
VDD1
LDO
ISOLATION
BARRIER
LDO
VDD2
DIN1+
DIN1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT1+
DOUT1–
DOUT2+
DOUT2–
GND1
VDD1
VIN1
ADN4651 LDO
Figure 1.
ISOLATION
BARRIER
VIN2
LDO
GND2
DIN1+
DIN1–
DOUT2+
DOUT2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DOUT1+
DOUT1–
DIN2+
DIN2–
GND1
VDD1
VIN1
ADN4652 LDO
Figure 2.
ISOLATION
BARRIER
VIN2
LDO
GND2
DOUT1+
DOUT1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DIN1+
DIN1–
DOUT2+
DOUT2–
GND1
Figure 3.
GND2
ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not
driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead,
wide body SOIC package with 5 kV rms isolation or a 20-lead
SSOP package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. E
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Tel: 781.329.4700 ©2015–2019 Analog Devices, Inc. All rights reserved.
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Analog Devices ADN4651
ADN4650/ADN4651/ADN4652
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagrams............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Receiver Input Threshold Test Voltages .................................... 4 
Timing Specifications .................................................................. 4 
Insulation and Safety Related Specifications ............................ 5 
Package Characteristics ............................................................... 6 
Regulatory Information............................................................... 6 
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics .............................................................................. 6 
Recommended Operating Conditions ...................................... 7 
Absolute Maximum Ratings............................................................ 8 
REVISION HISTORY
6/2019—Rev. D to Rev. E
Changes to Features Section............................................................ 1
Changed UL (Pending) Column to UL Column, CSA (Pending)
Column to CSA Column, VDE (Pending) Column to VDE
Column, Table 7, and DIN V VDE V 0884-10 (VDE V 0884-110)
Insulation Characteristics (Pending) Section to DIN V VDE V
0884-10 (VDE V 0884-110) Insulation Characteristics Section...... 6
1/2017—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 24
9/2016—Rev. B to Rev. C
Added 20-Lead SSOP.................................................... Throughout
Changes to Title, Features Section, and General Description .... 1
Added Table 5; Renumbered Sequentially .................................... 5
Change to Figure 5 ........................................................................... 7
Changes to PCB Layout Section ................................................... 19
Changes to Surface Tracking Section........................................... 20
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
4/2016—Rev. A to Rev. B
Added ADN4652 ................................................................Universal
Changes to Features Section and General Description Section....... 1
Added Figure 3; Renumbered Sequentially .................................. 1
Changes to Supply Current Parameter, Table 1 ............................ 3
Data Sheet
Thermal Resistance .......................................................................8 
ESD Caution...................................................................................8 
Pin Configurations and Function Descriptions ............................9 
Typical Performance Characteristics ........................................... 12 
Test Circuits and Switching Characteristics................................ 17 
Theory of Operation ...................................................................... 18 
Truth Table and Fail-Safe Receiver .......................................... 18 
Isolation ....................................................................................... 19 
PCB Layout ................................................................................. 19 
Magnetic Field Immunity.......................................................... 19 
Insulation Lifetime ..................................................................... 20 
Applications Information .............................................................. 22 
Outline Dimensions ....................................................................... 24 
Ordering Guide .......................................................................... 24 
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 .................................................................................................4
Changes to Table 12 ..........................................................................9
Moved Figure 7 ............................................................................... 10
Added Table 13 ............................................................................... 10
Added Figure 8 and Table 14, Renumbered Sequentially ......... 11
Changes to PCB Layout Section................................................... 19
Changes to Ordering Guide .......................................................... 24
2/2016—Rev. 0 to Rev. A
Added ADN4650 ................................................................Universal
Changes to Features Section and General Description Section........1
Added Figure 1; Renumbered Sequentially ...................................1
Changes to Supply Current Parameter, Table 1.............................3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 .................................................................................................4
Added Figure 5...................................................................................9
Changes to Table 12 ..........................................................................9
Changes to Figure 30 Caption and Figure 31 Caption .............. 14
Change to Figure 34 ....................................................................... 15
Changes to Truth Table and Fail-Safe Receiver Section............ 16
Added Table 13; Renumbered Sequentially ................................ 16
Change to Applications Information Section ............................. 20
Added Figure 41 ............................................................................. 20
Changes to Ordering Guide .......................................................... 22
11/2015—Revision 0: Initial Version
Rev. E | Page 2 of 25



Analog Devices ADN4651
Data Sheet
ADN4650/ADN4651/ADN4652
SPECIFICATIONS
For all minimum/maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = TMIN to TMAX, unless otherwise noted. For all typical
specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C.
Table 1.
Parameter
Symbol Min
Typ Max
Unit Test Conditions/Comments
INPUTS (RECEIVERS)
Input Threshold
See Figure 36 and Table 2
High
Low
VTH
VTL −100
100 mV
mV
Differential Input Voltage
Input Common-Mode Voltage
Input Current
Differential Input Capacitance1
|VID|
VIC
IIH, IIL
CINx±
100
0.5|VID|
−5
2
2.4 − 0.5|VID|
+5
mV
V
µA
pF
See Figure 36 and Table 2
See Figure 36 and Table 2
DINx± = VDD or 0 V, other input = 1.2 V, VDD = 2.5 V or 0 V
DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input = 1.2 V
OUTPUTS (DRIVERS)
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
VOS Peak-to-Peak1
Output Short-Circuit Current
|VOD|
|ΔVOD|
VOS
ΔVOS
VOS(PP)
IOS
Differential Output
Capacitance1
COUTx±
250
1.125
310 450
50
1.17 1.375
50
150
−20
12
5
mV See Figure 34 and Figure 35, RL = 100 Ω
mV See Figure 34 and Figure 35, RL = 100 Ω
V See Figure 34, RL = 100 Ω
mV See Figure 34, RL = 100 Ω
mV See Figure 34, RL = 100 Ω
mA DOUTx± = 0 V
mA |VOD| = 0 V
pF DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
POWER SUPPLY
Supply Current
ADN4651/ADN4652 Only
IDD1, IIN1,
IDD2, or IIN2
ADN4650 Only
LDO Input Range
LDO Output Range
Power Supply Ripple Rejection,
Phase Spur Level
VIN1 or
VIN2
VDD1 or
VDD2
PSRR
3.0
2.375
55
58 80
50 65
60 72
3.3 3.6
2.5 2.625
−75
mA No output load, inputs with 100 Ω, no applied |VID|
mA All outputs loaded, RL = 100 Ω, f = 300 MHz
mA No output load, inputs with 100 Ω, |VID| = 200 mV
mA All outputs loaded, RL = 100 Ω, f = 300 MHz
V No external supply on VDD1 or VDD2
V
dBc Phase spur level on DOUTx± with 300 MHz clock on
DINx± and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
COMMON-MODE TRANSIENT
|CM|
25
50
IMMUNITY2
kV/µs VCM = 1000 V, transient magnitude = 800 V
1 These specifications are guaranteed by design and characterization.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change on output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. E | Page 3 of 25







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