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Static RAM. CY7C109D Datasheet

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Static RAM. CY7C109D Datasheet






CY7C109D RAM. Datasheet pdf. Equivalent




CY7C109D RAM. Datasheet pdf. Equivalent





Part

CY7C109D

Description

1-Mbit (128 K x 8) Static RAM



Feature


CY7C109D CY7C1009D 1-Mbit (128 K × 8) S tatic RAM 1-Mbit (128 K × 8) Static R AM Features ■ Pin- and function-compa tible with CY7C109B/CY7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active po wer ❐ ICC = 80 mA at 10 ns ■ Low CM OS standby power ❐ ISB2 = 3 mA ■ 2. 0 V Data Retention ■ Automatic power- down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expans.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C109D Datasheet


Cypress Semiconductor CY7C109D

CY7C109D; ion with CE1, CE2 and OE options ■ CY7 C109D available in Pb-free 32-pin 400-M il wide Molded SOJ and 32-pin TSOP I pa ckages. CY7C1009D available in Pb-free 32-pin 300-Mil wide Molded SOJ package Functional Description The CY7C109D/CY7 C1009D [1] is a high-performance CMOS s tatic RAM organized as 131,072 words by 8 bits. Easy memory expansion is provi ded by an active LOW.


Cypress Semiconductor CY7C109D

Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enab le Logic Block Diagram (OE), and tri-s tate drivers.The eight input and output pins (I/O0 through I/O7) are placed in a high-impedance state when: ■ Dese .


Cypress Semiconductor CY7C109D

.

Part

CY7C109D

Description

1-Mbit (128 K x 8) Static RAM



Feature


CY7C109D CY7C1009D 1-Mbit (128 K × 8) S tatic RAM 1-Mbit (128 K × 8) Static R AM Features ■ Pin- and function-compa tible with CY7C109B/CY7C1009B ■ High speed ❐ tAA = 10 ns ■ Low active po wer ❐ ICC = 80 mA at 10 ns ■ Low CM OS standby power ❐ ISB2 = 3 mA ■ 2. 0 V Data Retention ■ Automatic power- down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expans.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C109D Datasheet




 CY7C109D
CY7C109D
CY7C1009D
1-Mbit (128 K × 8) Static RAM
1-Mbit (128 K × 8) Static RAM
Features
Pin- and function-compatible with CY7C109B/CY7C1009B
High speed
tAA = 10 ns
Low active power
ICC = 80 mA at 10 ns
Low CMOS standby power
ISB2 = 3 mA
2.0 V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE1, CE2 and OE options
CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available in
Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description
The CY7C109D/CY7C1009D [1] is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE1), an
active HIGH Chip Enable (CE2), an active LOW Output Enable
Logic Block Diagram
(OE), and tri-state drivers.The eight input and output pins (I/O0
through I/O7) are placed in a high-impedance state when:
Deselected (CE1 HIGH or CE2 LOW),
Outputs are disabled (OE HIGH),
When the write operation is active (CE1 LOW, CE2 HIGH, and
WE LOW)
Write to the device by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0 through
A16).
Read from the device by taking Chip Enable One (CE1) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE2) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the I/O pins.
The CY7C109D/CY7C1009D device is suitable for interfacing
with processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE1
CE2
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05468 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 16, 2015




 CY7C109D
CY7C109D
CY7C1009D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Document Number: 38-05468 Rev. *J
Page 2 of 16




 CY7C109D
Pin Configurations
Figure 1. 32-pin TSOP I pinout
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
TSOP I
Top View
(not to scale)
32 OE
31 A10
30 CE
29 I/O7
28 I/O6
27 I/O5
26
25
I/O4
I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
CY7C109D
CY7C1009D
Figure 2. 32-pin SOJ pinout (Top View) [2]
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 CE2
29 WE
28 A13
27
26
A8
A9
25 A11
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
CY7C109D-10
CY7C1009D-10
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05468 Rev. *J
Page 3 of 16



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