Reduced Latency. MT49H16M36 Datasheet

MT49H16M36 Latency. Datasheet pdf. Equivalent

MT49H16M36 Datasheet
Recommendation MT49H16M36 Datasheet
Part MT49H16M36
Description 576Mb CIO Reduced Latency
Feature MT49H16M36; 576Mb: x9 x18 x36 CIO RLDRAM 2 Features CIO RLDRAM 2 MT49H64M9 – 64 Meg x 9 x 8 Banks MT49H32M18 – .
Manufacture Micron
Datasheet
Download MT49H16M36 Datasheet




Micron MT49H16M36
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
CIO RLDRAM 2
MT49H64M9 – 64 Meg x 9 x 8 Banks
MT49H32M18 – 32 Meg x 18 x 8 Banks
MT49H16M36 – 16 Meg x 36 x 8 Banks
Features
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
– 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O
– 8 banks
• Reduced cycle time (15ns at 533 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time,
and burst sequence length
• Balanced READ and WRITE latencies in order to op-
timize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (16K refresh for each bank; 128K re-
fresh command must be issued in total each 32ms)
• HSTL I/O (1.5V or 1.8V nominal)
Ω matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT
Options1
• Clock cycle timing
– 1.875ns @ tRC = 15ns
– 2.5ns @ tRC = 15ns
– 2.5ns @ tRC = 20ns
– 3.3ns @ tRC = 20ns
• Configuration
– 64 Meg x 9
– 32 Meg x 18
– 16 Meg x 36
• Operating temperature
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)
• Package
– 144-ball μBGA
– 144-ball μBGA (Pb-free)
– 144-ball FBGA
– 144-ball FBGA (Pb-free)
• Revision
Marking
-18
-25E
-25
-33
64M9
32M18
16M36
None
IT
FM
BM
TR
SJ
:A/:B
Note:
1. Not all options listed can be combined to
define an offered product. Use the part cat-
alog search on www.micron.com for availa-
ble offerings.
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.



Micron MT49H16M36
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
BGA Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s web site at micron.com.
Figure 1: Part Numbers
Example Part Number: MT49H16M36SJ-25 :B
-:
MT49H
Configuration I/O Package Speed Temp. Rev.
Configuration
64 Meg x 9
32 Meg x 18
16 Meg x 36
64M9
32M18
16M36
I/O
Common None
Separate C
Package
144-ball μBGA
144-ball μBGA (Pb-free)
144-ball FBGA
144-ball FBGA (Pb-free)
FM
BM
TR
SJ
Revision
Rev. A
Rev. B
:A
:B
Temperature
Commercial
Industrial
None
IT
Speed Grade
-18 tCK = 1.875ns
-25E tCK = 2.5ns
-25 tCK = 2.5ns
-33 tCK = 3.3ns
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
2 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.



Micron MT49H16M36
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
Contents
General Description ......................................................................................................................................... 7
Functional Block Diagrams ............................................................................................................................... 8
Ball Assignments and Descriptions ................................................................................................................. 11
Package Dimensions ....................................................................................................................................... 16
Electrical Specifications – IDD .......................................................................................................................... 18
Absolute Maximum Ratings ............................................................................................................................ 22
AC and DC Operating Conditions .................................................................................................................... 23
Input Slew Rate Derating ................................................................................................................................ 26
Notes ............................................................................................................................................................. 31
Temperature and Thermal Impedance ............................................................................................................ 32
Commands .................................................................................................................................................... 34
MODE REGISTER SET (MRS) ...................................................................................................................... 35
Configuration Tables .............................................................................................................................. 37
Burst Length (BL) ................................................................................................................................... 37
Address Multiplexing .............................................................................................................................. 39
DLL RESET ............................................................................................................................................. 39
Drive Impedance Matching .................................................................................................................... 39
On-Die Termination (ODT) ..................................................................................................................... 40
WRITE ....................................................................................................................................................... 41
READ ......................................................................................................................................................... 42
AUTO REFRESH (AREF) .............................................................................................................................. 43
INITIALIZATION ............................................................................................................................................ 43
WRITE ........................................................................................................................................................... 47
READ ............................................................................................................................................................. 52
AUTO REFRESH ............................................................................................................................................. 60
On-Die Termination ....................................................................................................................................... 61
Multiplexed Address Mode .............................................................................................................................. 64
Address Mapping in Multiplexed Address Mode ........................................................................................... 67
Configuration Tables in Multiplexed Address Mode ...................................................................................... 67
REFRESH Command in Multiplexed Address Mode ..................................................................................... 68
IEEE 1149.1 Serial Boundary Scan (JTAG) ........................................................................................................ 72
Disabling the JTAG Feature ......................................................................................................................... 72
Test Access Port (TAP) ..................................................................................................................................... 72
Test Clock (TCK) ......................................................................................................................................... 72
Test Mode Select (TMS) .............................................................................................................................. 72
Test Data-In (TDI) ...................................................................................................................................... 73
Test Data-Out (TDO) .................................................................................................................................. 73
TAP Controller ................................................................................................................................................ 73
Test-Logic-Reset ......................................................................................................................................... 73
Run-Test/Idle ............................................................................................................................................. 73
Select-DR-Scan .......................................................................................................................................... 73
Capture-DR ................................................................................................................................................ 73
Shift-DR ..................................................................................................................................................... 73
Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 74
Update-DR ................................................................................................................................................. 74
Instruction Register States .......................................................................................................................... 74
Performing a TAP RESET ................................................................................................................................. 75
TAP Registers ................................................................................................................................................. 75
Instruction Register .................................................................................................................................... 75
Bypass Register .......................................................................................................................................... 75
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
3 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.







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