ODCSXX04 Datasheet: CMOS Gate Array





ODCSXX04 CMOS Gate Array Datasheet

Part Number ODCSXX04
Description CMOS Gate Array
Manufacture AMI
Total Page 2 Pages
PDF Download Download ODCSXX04 Datasheet PDF

Features: 2'&6;;[[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCSXXxx is a family of 4 to 24 mA, non-inverting, CMOS-lev el, output buffer pieces with controlle d slew rate outputs. Logic Symbol Tru th Table ODCSXXxx SL A PADM A PADM LL HH HDL Syntax Verilog ............... ..... ODCSXXxx inst_name (PADM, A); VHD L...................... inst_name: ODCS XXxx port map (PADM, A); Pin Loading Pin Name A (eq-load) ODCSXX04 9.3 Pow er Characteristics Cell Output Drive ( mA) ODCSXX04 4 ODCSXX08 8 ODCSXX12 12 ODCSXX16 16 ODCSXX24 24 a. Se e page 2-15 for power equation. ODCSXX 08 9.3 Load ODCSXX12 9.3 ODCSXX16 9.3 Power Characteristicsa Static IDD (T J = 85°C) (nA) TBD EQLpd (Eq-load) 19 8.6 TBD 220.0 TBD 240.8 TBD 263.6 TBD 282.3 ODCSXX24 11.4 Pad Logic 4-19 2'&6;;[[ $0,+*  PLFURQ &026 *DWH $UUD Propagation Delays (ns) Co nditions: TJ = 25°C, VDD = 5.0V, Typic al Process Capacitive Load (pF) 15 O DCSXX04 From: A tPLH To: PADM tPHL 2.46 2.44 Capacitive .

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2'&6;;[[
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$0,+*  PLFURQ &026 *DWH $UUD\
Description
ODCSXXxx is a family of 4 to 24 mA, non-inverting, CMOS-level, output buffer pieces with controlled slew rate outputs.
Logic Symbol
Truth Table
ODCSXXxx
SL
A
PADM
A PADM
LL
HH
HDL Syntax
Verilog .................... ODCSXXxx inst_name (PADM, A);
VHDL...................... inst_name: ODCSXXxx port map (PADM, A);
Pin Loading
Pin Name
A (eq-load)
ODCSXX04
9.3
Power Characteristics
Cell Output Drive (mA)
ODCSXX04
4
ODCSXX08
8
ODCSXX12
12
ODCSXX16
16
ODCSXX24
24
a. See page 2-15 for power equation.
ODCSXX08
9.3
Load
ODCSXX12
9.3
ODCSXX16
9.3
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
TBD
EQLpd (Eq-load)
198.6
TBD
220.0
TBD
240.8
TBD
263.6
TBD
282.3
ODCSXX24
11.4
4-19

     






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