80960JF Datasheet PDF Download, Intel





(PDF) 80960JF Datasheet Download

Part Number 80960JF
Description EMBEDDED 32-BIT MICROPROCESSOR
Manufacture Intel
Total Page 30 Pages
PDF Download Download 80960JF Datasheet PDF

Features: www.DataSheet4U.com A PRELIMINARY 809 60JA/JF EMBEDDED 32-BIT MICROPROCESSOR s Pin/Code Compatible with all 80960J x Processors s High-Performance Embedde d Architecture — One Instruction/Cloc k Execution — Load/Store Programming Model — Sixteen 32-Bit Global Registe rs — Sixteen 32-Bit Local Registers ( 8 sets) — Nine Addressing Modes — U ser/Supervisor Protection Model s High Bandwidth Burst Bus — 32-Bit Multipl exed Address/Data — Programmable Memo ry Configuration — Selectable 8-, 16- , 32-Bit Bus Widths — Supports Unalig ned Accesses — Big or Little Endian B yte Ordering s New Instructions — Con ditional Add, Subtract and Select — P rocessor Management s Two-Way Set Asso ciative Instruction Cache s High-Speed Interrupt Controller — 80960JA - 2 K byte — 80960JF - 4 Kbyte — Programm able Cache Locking — 31 Programmable Priorities — Eight Maskable Pins plu s NMI — Up to 240 Vectors in Expanded Mode Mechanism s Two On-Chip Timers s Direct Mapped Data Ca.

Keywords: 80960JF, datasheet, pdf, Intel, EMBEDDED, 32-BIT, MICROPROCESSOR, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute, Equivalent

www.DataSheet4U.com
A
PRELIMINARY
80960JA/JF
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
Processors
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model
s High Bandwidth Burst Bus
— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
s Two-Way Set Associative Instruction Cache s High-Speed Interrupt Controller
— 80960JA - 2 Kbyte
— 80960JF - 4 Kbyte
— Programmable Cache Locking
— 31 Programmable Priorities
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JA - 1 Kbyte
— 80960JF - 2 Kbyte
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
— Write Through Operation
s Halt Mode for Low Power
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
— 0-7 Frames Reserved for High-Priority s Packages
Interrupts
— 132-Lead Pin Grid Array (PGA)
s On-Chip Data RAM
— 132-Lead Plastic Quad Flat Pack (PQFP)
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
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PIN 1
132
33
A
i960®
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99
66
Figure 1. 80960JA/JF Microprocessors
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272504-004

                    
                    






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