CY2SSTV850
Differential Clock Buffer/Driver
Features
Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
1:10 differential outputs External Feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input SSCG: Spread Aware™ for EMI reduction 48-pin SSOP and TSSOP packages Conforms to JEDEC ...
