9LPRS502 Datasheet PDF | IDT





9LPRS502 Datasheet PDF Download

Part Number 9LPRS502
Description 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
Manufacture IDT
Total Page 29 Pages
PDF Download Download 9LPRS502 Datasheet PDF

Features: Datasheet 56-PIN CK505 W/FULLY INTEGRAT ED VOLTAGE REGULATOR + INTEGRATED SERIE S RESISTOR ICS9LPRS502 Recommended Ap plication: CK505 compliant clock with f ully integrated voltage regulator and I nternal series resistor on differential outputs, PCIe Gen 1 compliant Output F eatures: • 2 - CPU differential low p ower push-pull pairs • 7 - SRC differ ential low power push-pull pairs • 1 - CPU/SRC selectable differential low p ower push-pull pair • 1 - SRC/DOT sel ectable differential low power push-pul l pair • 5 - PCI, 33MHz • 1 - PCI_F , 33MHz free running • 1 - USB, 48MHz • 1 - REF, 14.318MHz Key Specificat ions: • CPU outputs cycle-cycle jitte r < 85ps • SRC output cycle-cycle jit ter < 125ps • PCI outputs cycle-cycle jitter < 250ps • +/- 100ppm frequenc y accuracy on CPU & SRC clocks Features /Benefits: • Does not require externa l pass transistor for voltage regulator • Integrated series resistors on dif ferential outputs, Zo=50W • Supports spread spectrum modulati.

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9LPRS502 datasheet
Datasheet
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE
REGULATOR + INTEGRATED SERIES RESISTOR
ICS9LPRS502
Recommended Application:
CK505 compliant clock with fully integrated voltage
regulator and Internal series resistor on differential outputs,
PCIe Gen 1 compliant
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7 - SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull
pair
• 1 - SRC/DOT selectable differential low power push-pull
pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on CPU & SRC
clocks
Features/Benefits:
• Does not require external pass transistor for voltage
regulator
• Integrated series resistors on differential outputs,
Zo=50W
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal
load caps are required for frequency tuning
• One differential push-pull pair selectable between
SRC and two single-ended outputs
Table 1: CPU Frequency Select Table
Pin Configuration
FSLC2 FSLB1 FSLA1
B0b7 B0b6 B0b5
CPU
MHz
SRC
MHz
PCI REF USB
MHz MHz MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66 100.00 33.33 14.318 48.00
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
111
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
DOT
MHz
96.00
PCICLK0/CR#_A 1
VDDPCI 2
PCICLK1/CR#_B 3
PCICLK2/LTE 4
PCICLK3 5
PCICLK4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96I/O 12
DOTT_96/SRCCLKT0 13
DOTC_96/SRCCLKC0 14
GND 15
VDD 16
SRCCLKT1/SE1 17
SRCCLKC1/SE2 18
GND 19
VDDPLL3I/O 20
SRCCLKT2/SATACLKT 21
SRCCLKC2/SATACLKC 22
GNDSRC 23
SRCCLKT3/CR#_C 24
SRCCLKC3/CR#_D 25
VDDSRCI/O 26
SRCCLKT4 27
SRCCLKC4 28
56 SCLK
55 SDATA
54 FSLC/TEST_SEL/REF0
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUCLKT0
45 CPUCLKC0
44 GNDCPU
43 CPUCLKT1
42 CPUCLKC1
41 VDDCPUI/O
40 NC
39 CPUCLKT2_ITP/SRCCLKT8
38 CPUCLKC2_ITP/SRCCLKC8
37 VDDSRCI/O
36 SRCCLKT7/CR#_F
35 SRCCLKC7/CR#_E
34 GNDSRC
33 SRCCLKT6
32 SRCCLKC6
31 VDDSRC
30 PCI_STOP#/SRCCLKT5
29 CPU_STOP#/SRCCLKC5
56-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor
1125E—02/26/09
1

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