Static RAM. CY7C106D Datasheet

CY7C106D RAM. Datasheet pdf. Equivalent

CY7C106D Datasheet
Recommendation CY7C106D Datasheet
Part CY7C106D
Description 1-Mbit (256K x 4) Static RAM
Feature CY7C106D; CY7C106D CY7C1006D 1-Mbit (256 K × 4) Static RAM 1-Mbit (256 K × 4) Static RAM Features ■ Pin- and .
Manufacture Cypress
Datasheet
Download CY7C106D Datasheet




Cypress CY7C106D
CY7C106D
CY7C1006D
1-Mbit (256 K × 4) Static RAM
1-Mbit (256 K × 4) Static RAM
Features
Pin- and function-compatible with CY7C106B/CY7C1006B
High speed
tAA = 10 ns
Low active power
ICC = 80 mA @ 10 ns
Low CMOS standby power
ISB2 = 3.0 mA
2.0 V Data Retention
Automatic power-down when deselected
CMOS for optimum speed/power
TTL-compatible inputs and outputs
CY7C106D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1006D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
Functional Description
The CY7C106D [1] and CY7C1006D [1] are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE), an active LOW Output Enable (OE), and tri-state drivers.
These devices have an automatic power-down feature that
reduces power consumption by more than 65% when the
devices are deselected. The four input and output pins (IO0
through IO3) are placed in a high-impedance state when:
Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is
then written into the location specified on the address pins (A0
through A17).
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appears on the four IO pins.
Both CY7C106D and CY7C1006D devices are suitable for
interfacing with processors that have TTL I/P levels. They are not
suitable for processors that require CMOS I/P levels. Please see
Electrical Characteristics on page 4 for more details and
suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
WE
OE
INPUT BUFFER
256K x 4
ARRAY
COLUMN DECODER
POWER
DOWN
IO0
IO1
IO2
IO3
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05459 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 26, 2014



Cypress CY7C106D
CY7C106D
CY7C1006D
Contents
Pin Configurations ........................................................... 3
Selection Guide ................................................................ 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions and Legal Information ....................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC® Solutions ...................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Document Number: 38-05459 Rev. *K
Page 2 of 16



Cypress CY7C106D
Pin Configurations
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum Standby Current
Figure 1. 28-pin SOJ pinout (Top View) [2]
A0
A1
A2
A3
A4
A5
A6
A7
A8
AA190
CE
OE
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 A17
26 A16
25 A15
24 A14
23 A13
22 A12
21 A11
20 NC
19 IO3
18 IO2
17 IO1
16 IO0
15 WE
Description
CY7C106D
CY7C1006D
CY7C106D-10
CY7C1006D-10
10
80
3
Unit
ns
mA
mA
Note
2. NC pins are not connected on the die.
Document Number: 38-05459 Rev. *K
Page 3 of 16







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