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Gigabit Isolators. ADN4654 Datasheet

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Gigabit Isolators. ADN4654 Datasheet






ADN4654 Isolators. Datasheet pdf. Equivalent




ADN4654 Isolators. Datasheet pdf. Equivalent





Part

ADN4654

Description

Dual-Channel LVDS Gigabit Isolators



Feature


Data Sheet 5 kV RMS and 3.75 kV RMS, Du al-Channel LVDS Gigabit Isolators ADN46 54/ADN4655/ADN4656 17011-001 FEATURES 5 kV rms and 3.75 kV rms LVDS isolator s Complies with TIA/EIA-644-A LVDS stan dard Multiple dual-channel configuratio ns Any data rate up to 1.1 Gbps switchi ng with low jitter 4 ns typical propaga tion delay 2.6 ps rms typical random ji tter, rms 90 ps ty.
Manufacture

Analog Devices

Datasheet
Download ADN4654 Datasheet


Analog Devices ADN4654

ADN4654; pical peak-to-peak total jitter at 1.1 G bps 2.5 V or 3.3 V supplies −75 dBc p ower supply ripple rejection, phase spu r level Glitch immunity ±8 kV IEC 6100 0-4-2 ESD protection across isolation b arrier High common-mode transient immun ity: >25 kV/μs Passes EN 55022 Class B radiated emissions limits with 1.1 Gbp s PRBS Safety and regulatory approvals (20-lead SOIC_W packag.


Analog Devices ADN4654

e) UL (pending): 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance N otice 5A (pending) VDE certificate of c onformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 424 VP EAK Fail-safe output high for open, sho rt, and terminated input conditions (AD N4655/ADN4656) Operating temperature ra nge: −40°C to +125°C 7.8 mm minimum creepage and clearanc.


Analog Devices ADN4654

e APPLICATIONS Isolated video and imagin g data Analog front-end isolation Data plane isolation Isolated high speed clo ck and data links FUNCTIONAL BLOCK DIA GRAMS VIN1 VIN2 ADN4654 VDD1 LDO I SOLATION BARRIER LDO VDD2 DIN1+ DIN1 – DIN2+ DIN2– LVDS DIGITAL ISOLAT OR LVDS DOUT1+ DOUT1– DOUT2+ DOUT2 GND1 VDD1 VIN1 ADN4655 LDO Figur e 1. ISOLATION BARRIER VI.

Part

ADN4654

Description

Dual-Channel LVDS Gigabit Isolators



Feature


Data Sheet 5 kV RMS and 3.75 kV RMS, Du al-Channel LVDS Gigabit Isolators ADN46 54/ADN4655/ADN4656 17011-001 FEATURES 5 kV rms and 3.75 kV rms LVDS isolator s Complies with TIA/EIA-644-A LVDS stan dard Multiple dual-channel configuratio ns Any data rate up to 1.1 Gbps switchi ng with low jitter 4 ns typical propaga tion delay 2.6 ps rms typical random ji tter, rms 90 ps ty.
Manufacture

Analog Devices

Datasheet
Download ADN4654 Datasheet




 ADN4654
Data Sheet
5 kV RMS and 3.75 kV RMS,
Dual-Channel LVDS Gigabit Isolators
ADN4654/ADN4655/ADN4656
FEATURES
5 kV rms and 3.75 kV rms LVDS isolators
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Any data rate up to 1.1 Gbps switching with low jitter
4 ns typical propagation delay
2.6 ps rms typical random jitter, rms
90 ps typical peak-to-peak total jitter at 1.1 Gbps
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection, phase spur level
Glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN 55022 Class B radiated emissions limits with
1.1 Gbps PRBS
Safety and regulatory approvals (20-lead SOIC_W package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 VPEAK
Fail-safe output high for open, short, and terminated input
conditions (ADN4655/ADN4656)
Operating temperature range: −40°C to +125°C
7.8 mm minimum creepage and clearance
APPLICATIONS
Isolated video and imaging data
Analog front-end isolation
Data plane isolation
Isolated high speed clock and data links
FUNCTIONAL BLOCK DIAGRAMS
VIN1
VIN2
ADN4654
VDD1
LDO
ISOLATION
BARRIER
LDO
VDD2
DIN1+
DIN1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT1+
DOUT1–
DOUT2+
DOUT2–
GND1
VDD1
VIN1
ADN4655 LDO
Figure 1.
ISOLATION
BARRIER
VIN2
LDO
GND2
DIN1+
DIN1–
DOUT2+
DOUT2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DOUT1+
DOUT1–
DIN2+
DIN2–
GND1
VDD1
VIN1
ADN4656 LDO
Figure 2.
ISOLATION
BARRIER
VIN2
LDO
GND2
DOUT1+
DOUT1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DIN1+
DIN1–
DOUT2+
DOUT2–
GENERAL DESCRIPTION
The ADN4654/ADN4655/ADN46561 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 1.1 Gbps with low jitter. The devices integrate Analog
Devices, Inc., iCoupler® technology, enhanced for high speed
operation to provide galvanic isolation of the TIA/EIA-644-A
compliant LVDS drivers and receivers. This integration allows
drop-in isolation of an LVDS signal chain.
The ADN4654/ADN4655/ADN4656 comprise multiple
channel configurations, and the LVDS receivers on the ADN4655
and ADN4656 include a fail-safe mechanism to ensure a Logic
GND1
Figure 3.
GND2
1 on the corresponding LVDS driver output when the inputs are
floating, shorted, or terminated but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
(LDO) regulator can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and come in a 20-lead, wide body
SOIC_W package with 5 kV rms isolation or in a 20-lead SSOP
package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. D
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




 ADN4654
ADN4654/ADN4655/ADN4656
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagrams............................................................. 1 
General Description ......................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Receiver Input Threshold Test Voltages .................................... 4 
Timing Specifications .................................................................. 4 
Insulation and Safety Related Specifications ............................ 5 
Package Characteristics ............................................................... 6 
Regulatory Information............................................................... 6 
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending)............................................................ 7 
Recommended Operating Conditions ...................................... 7 
Absolute Maximum Ratings............................................................ 8 
Thermal Resistance ...................................................................... 8 
REVISION HISTORY
9/2019—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 25
6/2019—Rev. B to Rev. C
Added ADN4656 ................................................................Universal
Changes to Features Section............................................................ 1
Added Figure 3; Renumbered Sequentially .................................. 1
Added Note 1, Table 8 ...................................................................... 7
Added Figure 8 and Table 15; Renumbered Sequentially ......... 11
Changes to Magnetic Field Immunity Section ........................... 22
Changes to Ordering Guide .......................................................... 25
3/2019—Rev. A to Rev. B
Changes to Title, Features Section, General Description
Section, and Figure 2........................................................................ 1
Changes to Table 4............................................................................ 5
Added Table 5.................................................................................... 5
Changes to Table 7............................................................................ 6
Changes to Table 8 and Figure 4..................................................... 7
Changes to Table 10, Table 11, and Table 12................................. 8
Added Figure 44.............................................................................. 23
Changes to Ordering Guide .......................................................... 23
Data Sheet
ESD Caution...................................................................................8 
Pin Configurations and Function Descriptions ............................9 
Typical Performance Characteristics ........................................... 12 
Test Circuits and Switching Characteristics................................ 17 
Theory of Operation ...................................................................... 18 
Truth Table and Fail-Safe Receiver .......................................... 18 
Isolation ....................................................................................... 19 
Applications Information .............................................................. 20 
PCB Layout ................................................................................. 20 
Application Examples ................................................................ 20 
Magnetic Field Immunity.......................................................... 22 
Insulation Lifetime ..................................................................... 22 
Outline Dimensions ....................................................................... 24 
Ordering Guide .......................................................................... 25 
1/2019—Rev. 0 to Rev. A
Added ADN4655 ................................................................Universal
Added Figure 2; Renumbered Sequentially ...................................1
Changes to General Description Section .......................................1
Changes to Table 1.............................................................................3
Changes to Table 3.............................................................................4
Added Timing Diagram Section and Figure 3 ..............................5
Changes to Figure 5 Caption and Table 12 Title ...........................9
Added Figure 6 and Table 13; Renumbered Sequentially ......... 10
Changes to Theory of Operation Section and Truth Table and
Fail Safe Receiver Section .............................................................. 17
Added Table 15 ............................................................................... 17
Moved Isolation Section ................................................................ 18
Moved PCB Layout Section .......................................................... 19
Changes to PCB Layout Section................................................... 19
Changes to Ordering Guide .......................................................... 23
11/2018—Revision 0: Initial Version
Rev. D | Page 2 of 25




 ADN4654
Data Sheet
ADN4654/ADN4655/ADN4656
SPECIFICATIONS
For all minimum and maximum specifications, VDD1 = VDD2 = 2.375 V to 2.625 V, TA = −40°C to +125°C, unless otherwise noted. For all
typical specifications, VDD1 = VDD2 = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol Min Typ Max
Unit Test Conditions/Comments
INPUTS (RECEIVERS)
Input Threshold
See Figure 38 and Table 2
High
Low
VTH
VTL −100
100 mV
mV
Differential Input Voltage
Input Common-Mode Voltage
Input Current, High and Low
|VID|
VIC
IIH, IIL
100
0.5|VID|
−5
2.4 − 0.5|VID|
+5
mV
V
μA
See Figure 38 and Table 2
See Figure 38 and Table 2
DINx± = VDDx or 0 V, other input = 1.2 V, VDDx =
2.5 V or 0 V
Differential Input Capacitance1 CINx±
2
pF DINx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V2
OUTPUTS (DRIVERS)
Differential Output Voltage |VOD|
250 310 450
mV See Figure 36 and Figure 37, load resistance (RL) =
100 Ω
VOD Magnitude Change
Offset Voltage
|ΔVOD|
VOS
1.125
50
1.17 1.375
mV See Figure 36 and Figure 37, RL = 100 Ω
V See Figure 36, RL = 100 Ω
VOS Magnitude Change
VOS, Peak to Peak1
Output Short-Circuit Current
ΔVOS
VOS(PP)
IOS
Differential Output
Capacitance1
COUTx±
50
150
−20
12
5
mV See Figure 36, RL = 100 Ω
mV See Figure 36, RL = 100 Ω
mA DOUTx± = 0 V
mA |VOD| = 0 V
pF DOUTx± = 0.4 sin(30 × 106πt) V + 0.5 V, other input =
1.2 V, VDD1 or VDD2 = 0 V
POWER SUPPLY
Supply Current
ADN4655/ADN4656 only
ADN4654 only
IDD1, IIN1,
IDD2, or IIN2
55
58 82
50 65
mA No output load, inputs with 100 Ω, no applied |VID|
mA All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
mA No output load, inputs with 100 Ω, |VID| = 200 mV
LDO Input Range
LDO Output Range
Power Supply Ripple Rejection,
Phase Spur Level
VIN1 or
VIN2
VDD1 or
VDD2
PSRR
3.0
2.375
60 80
3.3 3.6
2.5 2.625
−75
mA All outputs loaded, RL = 100 Ω, frequency = 0.55 GHz
V No external supply on VDD1 or VDD2
V
dBc Phase spur level on DOUTx± with 0.55 GHz clock on
DINx± and applied ripple of 100 kHz, 100 mV p-p on
a 2.5 V supply to VDD1 or VDD2
COMMON-MODE TRANSIENT |CM| 25 50
IMMUNITY3
kV/μs Common-mode voltage (VCM) = 1000 V, transient
magnitude = 800 V
1 These specifications are guaranteed by design and characterization.
2 t denotes time.
3 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining any DOUTx+/DOUTx− pin in the same state as the corresponding DINx+/DINx−
pin (no change in output), or producing the expected transition on any DOUTx+/DOUTx− pin if the applied common-mode transient edge is coincident with a data
transition on the corresponding DINx+/DINx− pin. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. D | Page 3 of 25



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