MC68HC68R1 RAMs Datasheet

MC68HC68R1 Datasheet PDF, Equivalent


Part Number

MC68HC68R1

Description

8-BIT SERIAL STATIC RAMs

Manufacture

Motorola

Total Page 3 Pages
Datasheet
Download MC68HC68R1 Datasheet


MC68HC68R1
® MOTOROLA
Advance Information
8-BIT SERIAL STATIC RAMs
The MC68HC68Rl and MC68HC68R2 are serially organized 128-word
(MC68HC68Rl) or 256-word (MC68HC68R2) by 8-bit static random ac-
cess memories (RAMs). These RAMs are intended for use in systems
where minimum package and interconnect size, low power, and
simplicity of use are desirable; for example, in systems utilizing syn-
chronous serial 3-wire (clock, data in, data out) interfaces. Interface can
I be made with the MC68HC05D2 without additional components, pro-
vided the MC68HC05D2 SPI control register bits CPHA and CPOL are
set.
• Fully Static Operation
• Operating Voltage Range: 3 V to 5.5 V
• Maximum Standby Current = 2 p,A
• Directly Compatible with SPI Interface
• Separate Data Input and Data Output Pins
• Input Data and Clock Buffers Gated Off with Chip Enable
• Protocol for Fast Sequential Multiple Byte Accesses
• Minimum Data Retention Voltage: 2 V
• Small 8-Lead Plastic Package
MC68HC68Rl
MC68HC68R2
HCMOS
(HIGH-DENSITY CMOS SILICON-GATE)
8-BIT SERIAL STATIC RAMs
P SUFFIX
PLASTIC PACKAGE
CASE 626
PIN ASSIGNMENT
S C K D 8 VDD
SS 2
7 SDI
See Note 3 .
VSS 4 ..
6 SDO
.5 CE
NOTE
Pin 3= N/C for MC68HC68Rl
Pin 3=A7 for MC68HC68R2
ThiS document contains InformAtion on ~ product under development Motorola reserves the
right to change or discontinue thIS product without notice
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MC68HC68R1
MC68HC68R1·MC68HC68R2
SIGNAL DESCRIPTION
CHIP ENABLE AND SLAVE SELECT (CE AND SS)
A high level on the CE pin, coincident with a low level on
the SS pin, is required for the RAM serial interface logic to
become enabled. The device is held in the reset state if either
CE is low or SS is high.
SERIAL CLOCK (SCK)
This clock input is used to synchronously latch data in and
shift data out of the RAM chip.
SERIAL DATA IN (SDI)
Serial data, present at this port, is latched into the RAM
chip by SCK if the chip is enabled and in a write cycle.
SERIAL DATA OUT (SDO)
Serial data is shifted out of this port by SCK if the RAM
chip is enabled and in a read cycle.
VDD AND VSS
The VOO pin is the + 5 volt power supply and VSS is the
ground reference pin.
ADDRESS LINE (A7) - MC68HC68R2 ONLY
This address input is used in the 256-word RAM version to
select either of two 128-word memory areas. (Address bits
AO-A6, used to provide the address within the 128-word
memory area in both the MC68HC68R1 and MC68HC68R2
versions, are the seven least significant bits of the first serial
8-bit byte received at the SOl port at the start of a read or
write cycle. The most significant bit of this first byte is the
read/write mode bit.)
DATA FORMAT, TRANSFER, AND TIMING
FORMAT
Two type of 8-bit bytes are used when storing or retrieving
data in the RAM chip, as shown in Figure 1.
FIGURE 1 - SERIAL DATA FORMAT
Addressl Control Byte
Bit: 7
4
I IRI W A6 A5 A4 A3 A2 A1 AO
AO-A6'
R/W:
The seven least significant RAM address bits, sufficient
to address 128 bytes.
Read or write data transfer control bit. R/W = 0 initiates
one or more memory read cycles; R/W = 1 initiates one
or more memory write cycles.
Data Byte
Bit· 4 3 2
D7 D6 D5 D4 D3 D2 D1 DO
DO-D7 8 bits of data
I
3-625


Features ® MOTOROLA Advance Information 8-BIT SE RIAL STATIC RAMs The MC68HC68Rl and MC6 8HC68R2 are serially organized 128-word (MC68HC68Rl) or 256-word (MC68HC68R2) by 8-bit static random access memories (RAMs). These RAMs are intended for use in systems where minimum package and i nterconnect size, low power, and simpli city of use are desirable; for example, in systems utilizing synchronous seria l 3-wire (clock, data in, data out) int erfaces. Interface can I be made with t he MC68HC05D2 without additional compon ents, provided the MC68HC05D2 SPI contr ol register bits CPHA and CPOL are set. • Fully Static Operation • Operati ng Voltage Range: 3 V to 5.5 V • Maxi mum Standby Current = 2 p,A • Directl y Compatible with SPI Interface • Sep arate Data Input and Data Output Pins Input Data and Clock Buffers Gated O ff with Chip Enable • Protocol for Fa st Sequential Multiple Byte Accesses Minimum Data Retention Voltage: 2 V Small 8-Lead Plastic Package MC68HC68Rl MC68HC68R2 HCMOS (HIGH-DENSITY CMOS SI.
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