TIMING GENERATOR. 9FGP202A Datasheet

9FGP202A GENERATOR. Datasheet pdf. Equivalent

9FGP202A Datasheet
Recommendation 9FGP202A Datasheet
Part 9FGP202A
Description FREQUENCY TIMING GENERATOR
Feature 9FGP202A; FREQUENCY TIMING GENERATOR FOR PERIPHERALS DATASHEET 9FGP202A General Description The 9FGP202A is .
Manufacture Renesas
Datasheet
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Renesas 9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
DATASHEET
9FGP202A
General Description
The 9FGP202A is a peripheral clock for Intel Server. It is
driven with a 25MHz crystal and generates CPU outputs up
to 400MHz. An SMBus interface allows full control of the
device.
Recommended Application
Peripheral Clock for Intel Server
Output Features
1 - 0.7V current-mode differential CPU pair
8 - 50MHz output
1 - DOT 96MHz output
1 - 33.33MHz output
1 - 32.768KHz output
2 - 25MHz REF outputs
Block Diagram
Features/Benefits
Selectable SMBus Address – D0/D1 or C0/C1
Spread Spectrum capability on CPU and DOT 96MHz
clocks
SMBus Control:
– M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
– Outputs can be disabled via pins or SMBus
Key Specifications
Exact synthesis on CPU, RMII and 33.33MHz clocks
+/- 100ppm frequency accuracy on remaining clocks
X1_25
X2_25
XTAL
CPU PLL
(SPREAD
CAPABLE)
25MHz(1:0)
CPUCLK
VttPwr_GD/PD#
OE_CPU
OE_96
OE_RMIIA
OE_RMIIB
SMBADR
SMBDAT
SMBCLK
CONTROL
LOGIC
DOT PLL
(SPREAD
CAPABLE)
FIXED
PLL
DIVIDERS
8
DIVIDERS
DOT96SS
33.33MHz
RMII(7:0)
32.768KHz
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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9FGP202A
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Renesas 9FGP202A
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Pin Configuration
40 39 38 37 36 35 34 33 32 31
GND 1
30 OE_RMIIB
VDD96 2
DOT96SST 3
29 RMII4
28 RMII5
DOT96SSC 4
27 GND RMII
OE_96 5
OE_CPU 6
9FGP202
26 VDDRMII
25 RMII6
CPUCLKT0 7
24 RMII7
CPUCLKC0 8
23 VDD33
VDDCPU 9
GNDCPU 10
22 33.33MHZ/**SMBADR
21 GND 33
11 12 13 14 15 16 17 18 19 20
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
SMBus Address Selection
SM BADR
*SMBADR = 0
D0/D1
* Default value
SMBADR = 1
C0 /C1
Power Supply Pins
Pin Number
VD D
GND
Des cription
9 10
21
CPUCLK output
DOT96SS output
26,34
23
27 ,35
21
50 MHz RMII outputs
33.33MHz output
12 14
15 18
32.768KHz output
XTAL, REF outputs
Note: All VDD should be connected to a common power rail with proper filtering
and decoupling.
Functionality
CPU FS2 CPU FS1 CPU FS0
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
P ower up default is highlighted.
CPUC LK
MHz
26 6.67
13 3.33
20 0.00
16 6.67
33 3.33
10 0.00
40 0.00
Reserved
DOT96SS
MH z
96.0 0
96.0 0
96.0 0
96.0 0
96.0 0
96.0 0
96.0 0
96.0 0
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
33 .33
MHz
33 .33
33 .33
33 .33
33 .33
33 .33
33 .33
33 .33
33 .33
RMII
MH z
50.0 0
50.0 0
50.0 0
50.0 0
50.0 0
50.0 0
50.0 0
50.0 0
25
MHz
2 5.00
2 5.00
2 5.00
2 5.00
2 5.00
2 5.00
2 5.00
2 5.00
2
32.76 8
KHz
32.7 68
32.7 68
32.7 68
32.7 68
32.7 68
32.7 68
32.7 68
32.7 68
9FGP202A
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Renesas 9FGP202A
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESC RIPTION
1 GND
2 VDD96
3 DOT96SST
4 DOT96SSC
5 OE_96
6 OE_CPU
7 CPUCLKT0
8 CPUCLKC0
9 VDDCPU
10 GNDCPU
11 IREF
12 VDD32K
13 32.768KHz
14 GND32K
15 VDDREF
16 25MHz_0
17 25MHZ_1
18 GNDREF
19 X1_25
20 X2_25
21 GND33
22 33.33MHZ/**SMBADR
23 VDD33
24 RMII7
25 RMII6
26 VDDRMII
27 GNDRMII
28 RMII5
29 RMII4
30 OE_RMIIB
31 OE_RMIIA
32 RMII3
33 RMII2
34 VDDRMII
35 GNDRMII
36 RMII1
37 RMII0
38 SMBCLK
39 SMBDAT
40 VttPwr_GD/PD#
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
OUT
PWR
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
Ground pin.
Power pin for the DOT96 cloc ks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock .
Complement clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
Ac tive high input for enabling 96Hz outputs.
1 = enable output(s ), 0 = tri-state output(s)
Ac tive high input for enabling CPU DIFF pairs.
1 = enable output(s ), 0 = tri-state output(s)
True clock of differential pair CPU outputs. These are c urrent mode outputs. External resistors are
required for voltage bias .
Complementary c lock of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision res istor tied to ground in order to establish the appropriate current. 475
ohms is the standard v alue.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs .
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz .
Ground pin for the 33.33MHz outputs
33.33MHz clock output / SMBus address select bit.
Power pin for the 33.33MHz outputs , nominal 3.3V
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Ac tive high input for enabling RMII(7:4) outputs.
1 = enable output(s ), 0 = low
Ac tive high input for enabling RMII(3:0) outputs.
1 = enable output(s ), 0 = low
3.3V RMII clock output
3.3V RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the 3V50 outputs
3.3V RMII clock output
3.3V RMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and
are ready to be sampled. This is an active high input. / Asynchronous activ e low input pin used to
power down the devic e into a low power state.
IDT® FREQUENCY TIMING GENERATOR FOR PERIPHERALS
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9FGP202A
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