POWER SELECTOR. bq24730 Datasheet
SLUS695 – MARCH 2006
ADVANCED MULTI-CHEMISTRY AND MULTI-CELL SYNCHRONOUS SWITCH-MODE
CHARGER AND SYSTEM POWER SELECTOR
• High Efficiency:
– NMOS-NMOS Synchronous Buck Converter
With Fixed 300 kHz Frequency
– Enhanced 6-V Drive Supply Voltage and
99.5% Max Duty Cycle
• High Voltage and Current Regulation
– 0.4% Charge Voltage Regulation Accuracy
– 4% Charge Current Regulation Accuracy
– 4% Adapter Current Regulation Accuracy
Dynamic Power Management (DPM)
• 3-Cell or 4-Cell Li-Ion Battery Voltage Select
• Programmable Battery Charge Current, and
AC Adapter Current via Resistor
• 2% Accurate Current Sense Amplifiers for
Both Input Current and Charge Current
• Input Current Sense Amplifier Can Be Enabled
with No Adapter to Sense Battery Discharge
• Regulates Charge Current Down to 0-V
• AC Adapter Operating Range 8 V–24 V
• Internal Soft Start
• Status Indicators:
– AC Adapter Present
– Low Battery Indicator
– DPM Regulation Loop Active Indicator
• Reverse Battery to Adapter Discharge
• Battery/Adapter to System Power Selector
• Charge Overcurrent Protection
• Available in 40-Pin 5x7mm QFN Package
• Portable Notebook Computers
• Portable DVD Players
• Webpads, PC Tablets
The bq24730 is a high efficiency synchronous battery
pack charger with high level of integration for portable
applications. This device implements a high
performance analog front-end that interfaces to the
system power management micro-controller through
a hardware interface.
The dynamic power management (DPM) function
modifies the charge current depending on system
load conditions, avoiding ac adapter overload.
High accuracy current sense amplifiers enable
accurate measurement of either the charge current or
the ac adapter current, allowing termination of
nonsmart packs and monitoring of overall system
power. The input current sense amplifier can be
enabled with no adapter to sense battery discharge
Integrated features such as charger soft start, charge
overcurrent protection, and IC temperature monitoring
provide a second level of protection, in addition to
pack and system protection functions.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SLUS695 – MARCH 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
5 x 7 mm QFN
(VERY LOW BATTERY
Charge Current Down to BAT = 0 V
(TAPE AND REEL)
PACKAGE THERMAL DATA
TA ≤ 40°C
ABOVE TA = 25°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
Charge enable logic level low input. Logic High (HI) on the CHGEN pin disables the charger. Logic Low (LO) on the
CHGEN pin enables the charger.
AC adapter to system switch driver output. Connect directly to the gate of the ACFET PMOS power FET. Connect the
FET source to the PVCC node and negative side of the input current-sense resistor. Connect the FET drain to the
system load side. Recommend placing a 10-kΩ resistor from the gate to the source of the AC FET to keep the FET off
when there is no power to the IC. If needed, an optional capacitor from gate to source of the ACFET is used to help
slow down the ON and OFF times. The internal gate drive is asymmetrical allowing a quick turn-off and slower turn-off
in addition to the internal break-before-make logic with respect to the BATDRV.
Adapter current sense resistor, negative input. An optional 0.1-µF ceramic capacitor is placed from this pin to AGND
for common-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN to ACP to provide
Adapter current sense resistor, positive input. Place this on the adapter side of the input current sense resistor.
Recommend placing a 0.1-µF ceramic capacitor from ACP to AGND to provide common-mode filtering.
AC adapter detected sense voltage input. Connect a voltage divider resistor from adapter input (before Bypass FET)
to ACDET, and another resistor from ACDET to AGND, in order to program adapter detect threshold of 2.4 V. ACDET
threshold should be greater than maximum battery regulation voltage, and lower than the minimum adapter voltage.
AC adapter (input) current limit setting. Program input current limit by a resistor from ACSET to AGND. Input current is
proportional to the current out of the ACSET pin.
Airline mode program pin. Program airline mode input voltage by a resistor divider between input voltage (before
BYPASS FET) and AGND. VREF5 regulator and system power selector (BYPASS pin and ACDRV pin) are enabled
500 ms after AIRDET voltage rises above 1.2 V. Charge is disabled until 500 ms after AIRDET voltage rises above 1.2
V, and 8 ms after ACDET rises above 2.4 V.
Gate drive for the adapter input BYPASS switch to prevent reverse discharge from the battery to the input. Connect
this pin directly to the gate of the input bypass PMOS power FET. The drain of the FET is connected to the adapter
input voltage node. The source of the FET is connected to the positive node of the input current-sense resistor.
Recommend placing a 10-kΩ resistor from the gate to the source of the BYPASS FET to keep the FET off when there
is no power to the IC. An optional capacitor can be placed from the gate to the source to slow-down the switching
times. Adjusting the turn-on and turn-off times is typically not needed for this FET.
Dynamic power management (DPM) input current loop active, open-drain output status. Logic low (LO) indicates input
current is being limited by reducing the charge current. A 10-kΩ pull-up resistor to the host controller supply rail is
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