OCTAL BUFFERS/DRIVERS. SN74AC240 Datasheet

SN74AC240 BUFFERS/DRIVERS. Datasheet pdf. Equivalent

SN74AC240 Datasheet
Recommendation SN74AC240 Datasheet
Part SN74AC240
Description OCTAL BUFFERS/DRIVERS
Feature SN74AC240; D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 6.5 ns at 5 V description/or.
Manufacture etcTI
Datasheet
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Texas Instruments SN74AC240
D 2-V to 6-V VCC Operation
D Inputs Accept Voltages to 6 V
D Max tpd of 6.5 ns at 5 V
description/ordering information
These octal buffers and line drivers are designed
specifically to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
The ’AC240 devices are organized as two 4-bit
buffers/drivers with separate output-enable (OE)
inputs. When OE is low, the device passes
inverted data from the A inputs to the Y outputs.
When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
SN54AC240, SN74AC240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS512E − JUNE 1995 − REVISED OCTOBER 2003
SN54AC240 . . . J OR W PACKAGE
SN74AC240 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1OE 1
1A1 2
2Y4 3
1A2 4
2Y3 5
1A3 6
2Y2 7
1A4 8
2Y1 9
GND 10
20 VCC
19 2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
SN54AC240 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1A2 4
18 1Y1
2Y3 5
17 2A4
1A3 6
16 1Y2
2Y2 7
15 2A3
1A4 8
14 1Y3
9 10 11 12 13
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube
SN74AC240N
SN74AC240N
SOIC − DW
Tube
Tape and reel
SN74AC240DW
SN74AC240DWR
AC240
−40°C to 85°C
SOP − NS
SSOP − DB
Tape and reel
Tape and reel
SN74AC240NSR
SN74AC240DBR
AC240
AC240
TSSOP − PW
CDIP − J
Tube
Tape and reel
Tube
SN74AC240PW
SN74AC240PWR
SNJ54AC240J
AC240
SNJ54AC240J
−55°C to 125°C CFP − W
Tube
SNJ54AC240W
SNJ54AC240W
LCCC − FK
Tube
SNJ54AC240FK
SNJ54AC240FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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Texas Instruments SN74AC240
SN54AC240, SN74AC240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS512E − JUNE 1995 − REVISED OCTOBER 2003
logic diagram (positive logic)
FUNCTION TABLE
(each buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
1
1OE
1A1 2
4
1A2
6
1A3
8
1A4
18 1Y1
16 1Y2
14 1Y3
12 1Y4
19
2OE
11
2A1
2A2 13
15
2A3
17
2A4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265



Texas Instruments SN74AC240
SN54AC240, SN74AC240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS512E − JUNE 1995 − REVISED OCTOBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54AC240 SN74AC240
UNIT
MIN MAX MIN MAX
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
Δt/Δv Input transition rise or fall rate
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
2
6
2
6V
2.1
2.1
3.15
3.15
V
3.85
3.85
0.9
0.9
1.35
1.35 V
1.65
1.65
0 VCC
0 VCC
−12
0 VCC
V
0 VCC
V
−12
−24
−24 mA
−24
−24
12
12
24
24 mA
24
24
8
8 ns/V
TA
Operating free-air temperature
−55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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