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D-A Converter. TLV5623 Datasheet

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D-A Converter. TLV5623 Datasheet






TLV5623 Converter. Datasheet pdf. Equivalent




TLV5623 Converter. Datasheet pdf. Equivalent





Part

TLV5623

Description

Low Power 8-Bit D-A Converter



Feature


TLV5623C, TLV5623I 2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG CONVER TERS WITH POWER DOWN SLAS231B − JUNE 1999 − REVISED APRIL 2004 D 8-Bit Vo ltage Output DAC D Programmable Settlin g Time vs Power Consumption 3 µs in Fa st Mode 9 µs in Slow Mode D Ultra Low Power Consumption: 900 µW Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V D Differential Nonlinearit.
Manufacture

Texas Instruments

Datasheet
Download TLV5623 Datasheet


Texas Instruments TLV5623

TLV5623; y . . . <0.2 LSB D Compatible With TMS32 0 and SPI Serial Ports D Power-Down Mod e D Buffered High-Impedance Reference Input D Monotonic Over Temperature D Av ailable in MSOP Package applications D Digital Servo Control Loops D Digital O ffset and Gain Adjustment D Industrial Process Control D Machine and Motion Co ntrol Devices D Mass Storage Devices d escription The TLV.


Texas Instruments TLV5623

5623 is a 8-bit voltage output digital-t oanalog converter (DAC) with a flexible 4-wire serial interface. The 4-wire se rial interface allows glueless interfac e to TMS320, SPI, QSPI, and Microwire s erial ports. The TLV5623 is programmed with a 16-bit serial string containing 4 control and 8 data bits. Developed fo r a wide range of supply voltages, the TLV5623 can operat.


Texas Instruments TLV5623

e from 2.7 V to 5.5 V. D OR DGK PACKAGE (TOP VIEW) DIN 1 SCLK 2 CS 3 FS 4 8 VDD 7 OUT 6 REFIN 5 AGND The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stag e to improve stability and reduce settl ing time. The settling time of the DAC is programmable to allow the designer t o optimize speed v.

Part

TLV5623

Description

Low Power 8-Bit D-A Converter



Feature


TLV5623C, TLV5623I 2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG CONVER TERS WITH POWER DOWN SLAS231B − JUNE 1999 − REVISED APRIL 2004 D 8-Bit Vo ltage Output DAC D Programmable Settlin g Time vs Power Consumption 3 µs in Fa st Mode 9 µs in Slow Mode D Ultra Low Power Consumption: 900 µW Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V D Differential Nonlinearit.
Manufacture

Texas Instruments

Datasheet
Download TLV5623 Datasheet




 TLV5623
TLV5623C, TLV5623I
2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG
CONVERTERS WITH POWER DOWN
SLAS231B − JUNE 1999 − REVISED APRIL 2004
D 8-Bit Voltage Output DAC
D Programmable Settling Time vs Power
Consumption
3 µs in Fast Mode
9 µs in Slow Mode
D Ultra Low Power Consumption:
900 µW Typ in Slow Mode at 3 V
2.1 mW Typ in Fast Mode at 3 V
D Differential Nonlinearity . . . <0.2 LSB
D Compatible With TMS320 and SPI Serial
Ports
D Power-Down Mode
D Buffered High-Impedance Reference Input
D Monotonic Over Temperature
D Available in MSOP Package
applications
D Digital Servo Control Loops
D Digital Offset and Gain Adjustment
D Industrial Process Control
D Machine and Motion Control Devices
D Mass Storage Devices
description
The TLV5623 is a 8-bit voltage output digital-to-
analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5623 is pro-
grammed with a 16-bit serial string containing 4
control and 8 data bits. Developed for a wide
range of supply voltages, the TLV5623 can
operate from 2.7 V to 5.5 V.
D OR DGK PACKAGE
(TOP VIEW)
DIN 1
SCLK 2
CS 3
FS 4
8 VDD
7 OUT
6 REFIN
5 AGND
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.
Implemented with a CMOS process, the TLV5623 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TLV5623C is characterized for operation from 0°C
to 70°C. The TLV5623I is characterized for operation from − 40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE†
MSOP
(D)
(DGK)
0°C to 70°C
TLV5623CD
TLV5623CDGK
−40°C to 85°C
TLV5623ID
TLV5623IDGK
Available in tape and reel as the TLV5623CDR and the TLV5623IDR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
WWW.TI.COM
Copyright 2002 − 2004, Texas Instruments Incorporated
1




 TLV5623
TLV5623C, TLV5623I
2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG
CONVERTERS WITH POWER DOWN
SLAS231B − JUNE 1999 − REVISED APRIL 2004
functional block diagram
_
6
REFIN
+
1
DIN
2
SCLK
3
CS
4
FS
Serial Input
10
Register
16 Cycle
Timer
Update
8
8-Bit
Data
8
Latch
x2
7
OUT
Power-On
Reset
2
Speed/Power-Down
Logic
Terminal Functions
TERMINAL
NAME NO.
AGND
5
CS
3
DIN
1
FS
4
OUT
7
REFIN
6
SCLK
2
VDD
8
I/O
DESCRIPTION
Analog ground
I Chip select. Digital input used to enable and disable inputs, active low.
I Serial digital data input
I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
O DAC analog output
I Reference analog input voltage
I Serial digital clock input
Positive power supply
2
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 TLV5623
TLV5623C, TLV5623I
2.7ĆV TO 5.5ĆV LOW POWER 8ĆBIT DIGITALĆTOĆANALOG
CONVERTERS WITH POWER DOWN
SLAS231B − JUNE 1999 − REVISED APRIL 2004
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA: TLV5623C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV5623I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
Supply voltage, VDD
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Reference voltage, Vref to REFIN terminal
Reference voltage, Vref to REFIN terminal
Load resistance, RL
Load capacitance, CL
Clock frequency, fCLK
Operating free-air temperature, TA
VDD = 5 V
VDD = 3 V
DVDD = 2.7 V
DVDD = 5.5 V
DVDD = 2.7 V
DVDD = 5.5 V
VDD = 5 V (see Note 1)
VDD = 3 V (see Note 1)
TLV5623C
TLV5623I
4.5
5
2.7
3
2
2.4
AGND
AGND
2
2.048
1.024
10
0
− 40
NOTE 1: Due to the x2 output buffer, a reference input voltage VDD/2 causes clipping of the transfer function.
MAX
5.5
3.3
0.6
1
VDD −1.5
VDD −1.5
100
20
70
85
UNIT
V
V
V
V
V
V
V
V
k
pF
MHz
°C
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
IDD
Power supply current
VDD = 5 V, VREF = 2.048 V,
No load,
All inputs = AGND or VDD,
DAC latch = 0x800
VDD = 3 V, VREF = 1.024 V
No load,
All inputs = AGND or VDD,
DAC latch = 0x800
Fast
Slow
Fast
Slow
Power down supply current (see Figure 12)
PSRR Power supply rejection ratio
Zero scale See Note 2
Full scale See Note 3
Power on threshold voltage, POR
NOTES:
2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) − EZS(VDDmin))/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) − EG(VDDmin))/VDDmax]
MIN TYP MAX UNIT
0.9 1.35 mA
0.4 0.6 mA
0.7 1.1 mA
0.3 0.45 mA
1
µA
−68
dB
−68
2
V
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3



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