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Digital-to-Analog Converter. TLV5625 Datasheet

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Digital-to-Analog Converter. TLV5625 Datasheet






TLV5625 Converter. Datasheet pdf. Equivalent




TLV5625 Converter. Datasheet pdf. Equivalent





Part

TLV5625

Description

Low-Power Dual 8-Bit Digital-to-Analog Converter



Feature


TLV5625 2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 8ĆBIT DIGITALĆTOĆANALOG CONVERTER W ITH POWER DOWN SLAS233D − JULY 1999 REVISED JULY 2002 features D Dual 8 -Bit Voltage Output DAC D Programmable Internal Reference D Programmable Settl ing Time − 3 µs in Fast Mode − 10 µs in Slow Mode D Compatible With TMS3 20 and SPI Serial Ports D Differenti al Nonlinearity <0.2 LSB Max D Monot.
Manufacture

Texas Instruments

Datasheet
Download TLV5625 Datasheet


Texas Instruments TLV5625

TLV5625; onic Over Temperature applications D Di gital Servo Control Loops D Digital Off set and Gain Adjustment D Industrial Pr ocess Control D Machine and Motion Cont rol Devices D Mass Storage Devices D PA CKAGE (TOP VIEW) description The TLV56 25 is a dual 8-bit voltage output DAC w ith a flexible 3-wire serial interface. The serial interface is compatible wit h TMS320, SPI, QS.


Texas Instruments TLV5625

PI, and Microwire serial ports. It is programmed with a 16-bit serial str ing containing 4 control and 8 data bit s. DIN 1 SCLK 2 CS 3 OUTA 4 8 VDD 7 O UTB 6 REF 5 AGND The resistor string o utput voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class-AB output stage to im prove stability and reduce settling tim e. The programmable se.


Texas Instruments TLV5625

ttling time of the DAC allows the design er to optimize speed versus power dissi pation. Implemented with a CMOS proces s, the device is designed for single su pply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package i n standard commercial and industrial te mperature ranges. AVAILABLE OPTIONS P ACKAGE TA SOIC (D) 0°C to 70°C T LV5625CD −40°C to 8.

Part

TLV5625

Description

Low-Power Dual 8-Bit Digital-to-Analog Converter



Feature


TLV5625 2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 8ĆBIT DIGITALĆTOĆANALOG CONVERTER W ITH POWER DOWN SLAS233D − JULY 1999 REVISED JULY 2002 features D Dual 8 -Bit Voltage Output DAC D Programmable Internal Reference D Programmable Settl ing Time − 3 µs in Fast Mode − 10 µs in Slow Mode D Compatible With TMS3 20 and SPI Serial Ports D Differenti al Nonlinearity <0.2 LSB Max D Monot.
Manufacture

Texas Instruments

Datasheet
Download TLV5625 Datasheet




 TLV5625
TLV5625
2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 8ĆBIT DIGITALĆTOĆANALOG
CONVERTER WITH POWER DOWN
SLAS233D − JULY 1999 − REVISED JULY 2002
features
D Dual 8-Bit Voltage Output DAC
D Programmable Internal Reference
D Programmable Settling Time
− 3 µs in Fast Mode
− 10 µs in Slow Mode
D Compatible With TMS320 and SPISerial
Ports
D Differential Nonlinearity <0.2 LSB Max
D Monotonic Over Temperature
applications
D Digital Servo Control Loops
D Digital Offset and Gain Adjustment
D Industrial Process Control
D Machine and Motion Control Devices
D Mass Storage Devices
D PACKAGE
(TOP VIEW)
description
The TLV5625 is a dual 8-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface is compatible with TMS320, SPI,
QSPI, and Microwireserial ports. It is pro-
grammed with a 16-bit serial string containing 4
control and 8 data bits.
DIN 1
SCLK 2
CS 3
OUTA 4
8 VDD
7 OUTB
6 REF
5 AGND
The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a
Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC
allows the designer to optimize speed versus power dissipation.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS
PACKAGE
TA
SOIC
(D)
0°C to 70°C
TLV5625CD
−40°C to 85°C
TLV5625ID
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1




 TLV5625
TLV5625
2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 8ĆBIT DIGITALĆTOĆANALOG
CONVERTER WITH POWER DOWN
SLAS233D − JULY 1999 − REVISED JULY 2002
functional block diagram
REF AGND VDD
Power-On
Reset
Power and
Speed Control
2
DIN
SCLK
CS
8
8-Bit
8
DAC A
Serial
Interface
8
Latch
and
Control
Buffer
8
8
8-Bit
DAC B
Latch
x2
OUTA
x2
OUTB
TERMINAL
NAME
NO.
AGND
5
CS
3
DIN
1
OUTA
4
OUTB
7
REF
6
SCLK
2
VDD
8
Terminal Functions
I/O/P
DESCRIPTION
P Ground
I Chip select. Digital input active low, used to enable/disable inputs.
I Digital serial data input
O DAC A analog voltage output
O DAC B analog voltage output
I Analog reference voltage input
I Digital serial clock input
P Positive power supply
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




 TLV5625
TLV5625
2.7ĆV TO 5.5ĆV LOWĆPOWER DUAL 8ĆBIT DIGITALĆTOĆANALOG
CONVERTER WITH POWER DOWN
SLAS233D − JULY 1999 − REVISED JULY 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA: TLV5625C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
TLV5625I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX
Supply voltage, VDD
Power on reset, POR
VDD = 5 V
VDD = 3 V
4.5
5
5.5
2.7
3
3.3
0.55
2
High-level digital input voltage, VIH
Low-level digital input voltage, VIL
Reference voltage, Vref to REF terminal
Load resistance, RL
Load capacitance, CL
Clock frequency, fCLK
Operating free-air temperature, TA
VDD = 2.7 V
VDD = 5.5 V
VDD = 2.7 V
VDD = 5.5 V
VDD = 5 V (see Note 1)
VDD = 3 V (see Note 1)
TLV5625C
TLV5625I
2
2.4
AGND
AGND
2
0
−40
2.048
1.024
0.6
1
VDD −1.5
VDD −1.5
100
20
70
85
NOTE 1: Due to the x2 output buffer, a reference input voltage (VDD−0.4 V)/2 causes clipping of the transfer function.
UNIT
V
V
V
V
V
V
k
pF
MHz
°C
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3






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