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Positive-OR Gate. SN74AUC1G32 Datasheet

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Positive-OR Gate. SN74AUC1G32 Datasheet






SN74AUC1G32 Gate. Datasheet pdf. Equivalent




SN74AUC1G32 Gate. Datasheet pdf. Equivalent





Part

SN74AUC1G32

Description

Single 2-Input Positive-OR Gate



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74AUC1G32 SCES377P – SEPTEM BER 2001 – REVISED JUNE 2017 SN74AUC1 G32 Single 2-Input Positive-OR Gate 1 Features •1 Latch-Up Performance Exce eds 100 mA Per JESD 78, Class II • ES D Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V C harged-Device Model (C101) • A.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G32 Datasheet


Texas Instruments SN74AUC1G32

SN74AUC1G32; vailable in the Texas Instruments NanoFr ee™ Package • Optimized for 1.8-V O peration and Is 3.6-V I/O Tolerant to S upport Mixed-Mode Signal Operation • Ioff Partial-Power-Down Mode and Back D rive Protection • Sub-1-V Operable Max tpd of 2.4 ns at 1.8 V • Low Po wer Consumption, 10-μA Maximum ICC • ±8-mA Output Drive at 1.8 V 2 Applica tions • AV Receiver • Audio Dock: .


Texas Instruments SN74AUC1G32

Portable • Blu-ray Player and Home The ater • Embedded PC • MP3 Player/Rec order (Portable Audio) • Personal Dig ital Assistant (PDA) • Power: Telecom /Server AC/DC Supply: Single Controller : Analog and Digital • Solid State Dr ive (SSD): Client and Enterprise • TV : LCD/Digital and High-Definition (HDTV ) • Tablet: Enterprise • Video Anal ytics: Server • Wireless Headset, Ke.


Texas Instruments SN74AUC1G32

yboard, and Mouse 3 Description This si ngle 2-input positive-OR gate is operat ional at 0.8-V to 2.7-V VCC, but is des igned specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC1G32 device performs the Boolean function Y + A ) B or Y + A · B in positive logic. NanoF ree™ package technology is a major br eakthrough in IC packaging concepts, us ing the die as the pa.

Part

SN74AUC1G32

Description

Single 2-Input Positive-OR Gate



Feature


Product Folder Order Now Technical Doc uments Tools & Software Support & Com munity SN74AUC1G32 SCES377P – SEPTEM BER 2001 – REVISED JUNE 2017 SN74AUC1 G32 Single 2-Input Positive-OR Gate 1 Features •1 Latch-Up Performance Exce eds 100 mA Per JESD 78, Class II • ES D Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 1000-V C harged-Device Model (C101) • A.
Manufacture

Texas Instruments

Datasheet
Download SN74AUC1G32 Datasheet




 SN74AUC1G32
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SN74AUC1G32
SCES377P – SEPTEMBER 2001 – REVISED JUNE 2017
SN74AUC1G32 Single 2-Input Positive-OR Gate
1 Features
1 Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
• Available in the Texas Instruments NanoFree™
Package
• Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
• Ioff Partial-Power-Down Mode and Back Drive
Protection
• Sub-1-V Operable
• Max tpd of 2.4 ns at 1.8 V
• Low Power Consumption, 10-μA Maximum ICC
• ±8-mA Output Drive at 1.8 V
2 Applications
• AV Receiver
• Audio Dock: Portable
• Blu-ray Player and Home Theater
• Embedded PC
• MP3 Player/Recorder (Portable Audio)
• Personal Digital Assistant (PDA)
• Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
• Solid State Drive (SSD): Client and Enterprise
• TV: LCD/Digital and High-Definition (HDTV)
• Tablet: Enterprise
• Video Analytics: Server
• Wireless Headset, Keyboard, and Mouse
3 Description
This single 2-input positive-OR gate is operational at
0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUC1G32 device performs the Boolean
function Y + A ) B or Y + A · B in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
For more information about AUC Little Logic devices,
see Applications of Texas Instruments AUC Sub-1-V
Little Logic Devices, SCEA027.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74AUC1G32DBV SOT-23 (5)
2.90 mm × 1.60 mm
SN74AUC1G32DCK SC70 (5)
2.00 mm × 1.25 mm
SN74AUC1G32DRL SOT-5X3 (5)
1.60 mm × 1.20 mm
SN74AUC1G32YZP DSBGA (5)
1.39 mm × 0.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.




 SN74AUC1G32
SN74AUC1G32
SCES377P – SEPTEMBER 2001 – REVISED JUNE 2017
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics: CL = 15 pF ...................... 5
6.7 Switching Characteristics: CL = 30 pF ...................... 5
6.8 Operating Characteristics.......................................... 6
7 Parameter Measurement Information .................. 7
8 Detailed Description .............................................. 8
8.1 Functional Block Diagram ......................................... 8
8.2 Device Functional Modes.......................................... 8
9 Device and Documentation Support.................... 9
9.1 Documentation Support ........................................... 9
9.2 Receiving Notification of Documentation Updates.... 9
9.3 Community Resources.............................................. 9
9.4 Trademarks ............................................................... 9
9.5 Electrostatic Discharge Caution ................................ 9
9.6 Glossary .................................................................... 9
10 Mechanical, Packaging, and Orderable
Information ............................................................. 9
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (September 2009) to Revision P
Page
• Added Application section, Pin Configuration and Functions section, ESD Ratings table, Feature Description
section, Device Functional Modes, Application and Implementation Power Supply Recommendations section,
Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section. .................................................................................................................................................................................. 1
• Deleted Ordering Information table, see Mechanical, Packaging, and Orderable Information at the end of the data sheet. 1
• Deleted DRY package throughout data sheet........................................................................................................................ 1
Changes from Revision N (September 2001) to Revision O
Page
• Updated document to new TI data sheet format - no specification changes. ........................................................................ 1
• Removed Ordering Information. ............................................................................................................................................. 1
2
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Copyright © 2001–2017, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G32




 SN74AUC1G32
www.ti.com
5 Pin Configuration and Functions
DBV Package
SOT-23
Top View
A
1
5
VCC
B
2
GND
3
4
Y
DCK Package
5-Pin SC70
Top View
A
1
5
VCC
B
2
GND
3
4Y
See mechanical drawings for dimensions.
NC No internal connections
NAME
A
B
GND
VCC
Y
PIN
DBV, DCK,
DRL
YZP
1
A1
2
B1
3
C1
5
A2
4
C2
Pin Functions
I/O
I
Input A
I
Input B
— Ground
— Positive Supply
O Output Y
SN74AUC1G32
SCES377P – SEPTEMBER 2001 – REVISED JUNE 2017
DRL Package
5-Pin SOT-5X3
Top View
A1
B2
GND 3
5 VCC
4Y
YZP Package
5-Pin DSBGA
Bottom View
1
2
C GND
Y
B
B
A
A
VCC
Not to scale
DESCRIPTION
Copyright © 2001–2017, Texas Instruments Incorporated
Product Folder Links: SN74AUC1G32
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