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x 8-bit. HM628511HI Datasheet |
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HM628511HI Series
4M High Speed SRAM (512-kword × 8-bit)
ADE-203-1035A (Z)
Rev. 1.0
Apr. 15, 1999
Description
The HM628511HI Series is a 4-Mbit high speed static RAM organized 512-k word × 8-bit. It has realized
high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high
speed circuit designing technology. It is most appropriate for the application which requires high speed, high
density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged
in 400-mil 36-pin plastic SOJ.
Features
• Single 5.0 V supply : 5.0 V ± 10 %
• Access time 12 /15 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current : 160 / 140 mA (max)
• TTL standby current : 60 / 50 mA (max)
• CMOS standby current : 5 mA (max)
• Center VCC and VSS type pinout
• Temperature range: –40 to 85°C
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HM628511HI Series
Ordering Information
Type No.
HM628511HJPI-12
HM628511HJPI-15
Access time
12 ns
15 ns
Package
400-mil 36-pin plastic SOJ (CP-36D)
Pin Arrangement
HM628511HJPI Series
A0 1
A1 2
A2 3
A3 4
A4 5
CS 6
I/O1 7
I/O2 8
VCC
9
VSS
I/O3
10
11
I/O4 12
WE 13
A5 14
A6 15
A7 16
A8 17
A9 18
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE
30 I/O8
29 I/O7
28 VSS
27 VCC
26 I/O6
25 I/O5
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
(Top View)
2
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Pin Description
Pin name
A0 to A18
I/O1 to I/O8
CS
OE
WE
VCC
VSS
NC
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
No connection
HM628511HI Series
Block Diagram
(LSB)
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
I/O1
.
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.
I/O8
WE
CS
Row
decoder
Memory matrix
256 rows × 8 columns ×
256 blocks × 8 bit
(4,194,304 bits)
Internal
voltage
generater
VCC
VSS
CS
Input
data
control
Column I/O
Column decoder
CS
A10 A8 A9 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
(MSB)
OE
CS
3
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